From 4894bddce062de7163e61f17a41dbed50d8fdd2f Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Thu, 28 Mar 2019 10:20:28 -0400 Subject: [PATCH] gpu: nvgpu: sec2: fix MISRA 10.3 violations MISRA Rule 10.3 prohibits assignment of objects of different essential or narrower type. This fixes a number of MISRA 10.3 violations in common/sec2 unit. JIRA NVGPU-2957 Change-Id: Ie10261f26dbc44e9e69122ef9f6edf8cbc2fab92 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2083943 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/sec2/sec2.c | 12 ++++++++---- drivers/gpu/nvgpu/common/sec2/sec2_ipc.c | 16 +++++++++------- drivers/gpu/nvgpu/include/nvgpu/sec2.h | 2 +- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/common/sec2/sec2.c b/drivers/gpu/nvgpu/common/sec2/sec2.c index 520fe731d..584051bf8 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -233,14 +234,17 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, bool command_ack; u32 seq = 0; int err = 0; + size_t tmp_size; nvgpu_log_fn(g, " "); /* send message to load falcon */ (void) memset(&cmd, 0, sizeof(struct nv_flcn_cmd_sec2)); cmd.hdr.unit_id = NV_SEC2_UNIT_ACR; - cmd.hdr.size = PMU_CMD_HDR_SIZE + + tmp_size = PMU_CMD_HDR_SIZE + sizeof(struct nv_sec2_acr_cmd_bootstrap_falcon); + nvgpu_assert(tmp_size <= U64(U8_MAX)); + cmd.hdr.size = U8(tmp_size); cmd.cmd.acr.bootstrap_falcon.cmd_type = NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON; @@ -252,13 +256,13 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, command_ack = false; err = nvgpu_sec2_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_HPQ, - sec2_handle_lsfm_boot_acr_msg, &command_ack, &seq, ~0UL); + sec2_handle_lsfm_boot_acr_msg, &command_ack, &seq, U32_MAX); if (err != 0) { nvgpu_err(g, "command post failed"); } err = nvgpu_sec2_wait_message_cond(sec2, nvgpu_get_poll_timeout(g), - &command_ack, true); + &command_ack, U8(true)); if (err != 0) { nvgpu_err(g, "command ack receive failed"); } @@ -275,7 +279,7 @@ int nvgpu_sec2_bootstrap_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, nvgpu_sec2_dbg(g, "Check SEC2 RTOS is ready else wait"); err = nvgpu_sec2_wait_message_cond(&g->sec2, nvgpu_get_poll_timeout(g), - &g->sec2.sec2_ready, true); + &g->sec2.sec2_ready, U8(true)); if (err != 0){ nvgpu_err(g, "SEC2 RTOS not ready yet, failed to bootstrap flcn %d", falcon_id); diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c index 0a18042e6..f2a781d5b 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -35,7 +36,7 @@ static int sec2_seq_acquire(struct nvgpu_sec2 *sec2, { struct gk20a *g = sec2->g; struct sec2_sequence *seq; - u32 index = 0; + u64 index = 0; int err = 0; nvgpu_mutex_acquire(&sec2->sec2_seq_lock); @@ -50,7 +51,8 @@ static int sec2_seq_acquire(struct nvgpu_sec2 *sec2, goto exit; } - set_bit(index, sec2->sec2_seq_tbl); + nvgpu_assert(index < U64(INT_MAX)); + set_bit((int)index, sec2->sec2_seq_tbl); nvgpu_mutex_release(&sec2->sec2_seq_lock); @@ -74,7 +76,7 @@ static void sec2_seq_release(struct nvgpu_sec2 *sec2, seq->msg = NULL; seq->out_payload = NULL; - clear_bit(seq->id, sec2->sec2_seq_tbl); + clear_bit((int)seq->id, sec2->sec2_seq_tbl); } /* command post operation functions */ @@ -115,7 +117,7 @@ invalid_cmd: static int sec2_write_cmd(struct nvgpu_sec2 *sec2, struct nv_flcn_cmd_sec2 *cmd, u32 queue_id, - unsigned long timeout_ms) + u32 timeout_ms) { struct gk20a *g = sec2->g; struct nvgpu_engine_mem_queue *queue; @@ -146,7 +148,7 @@ static int sec2_write_cmd(struct nvgpu_sec2 *sec2, int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd, struct nv_flcn_msg_sec2 *msg, u32 queue_id, sec2_callback callback, - void *cb_param, u32 *seq_desc, unsigned long timeout) + void *cb_param, u32 *seq_desc, u32 timeout) { struct nvgpu_sec2 *sec2 = &g->sec2; struct sec2_sequence *seq = NULL; @@ -275,7 +277,7 @@ static bool sec2_read_message(struct nvgpu_sec2 *sec2, u32 read_size; int err; - *status = 0U; + *status = 0; if (nvgpu_engine_mem_queue_is_empty(queue)) { return false; @@ -435,7 +437,7 @@ int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms, { struct gk20a *g = sec2->g; struct nvgpu_timeout timeout; - unsigned long delay = POLL_DELAY_MIN_US; + u32 delay = POLL_DELAY_MIN_US; nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER); diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2.h index 4ee516f19..dbd968039 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2.h @@ -97,7 +97,7 @@ struct nvgpu_sec2 { /* command/message handling methods*/ int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd, struct nv_flcn_msg_sec2 *msg, u32 queue_id, sec2_callback callback, - void *cb_param, u32 *seq_desc, unsigned long timeout); + void *cb_param, u32 *seq_desc, u32 timeout); int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2); int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms, void *var, u8 val);