diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c
index d8786b8f5..b9a5f58b9 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon.c
@@ -19,10 +19,10 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#include <nvgpu/lock.h>
-#include <nvgpu/timers.h>
-#include <nvgpu/falcon.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/timers.h>
+
+#include "falcon_priv.h"
 
 /* Delay depends on memory size and pwr_clk
  * delay = (MAX {IMEM_SIZE, DMEM_SIZE} * 64 + 1) / pwr_clk
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c
index 80c0b936b..2c0aff1ae 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c
@@ -19,12 +19,12 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#include <nvgpu/falcon.h>
 #include <nvgpu/pmu.h>
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
 
 #include "falcon_gk20a.h"
+#include "falcon_priv.h"
 
 #include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
 
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c b/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c
index 2b6f1725e..321028db0 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,10 +23,9 @@
 
 #include "falcon_gk20a.h"
 #include "falcon_gp106.h"
+#include "falcon_priv.h"
 #include "gp106/sec2_gp106.h"
 
-#include <nvgpu/hw/gp106/hw_falcon_gp106.h>
-
 static void gp106_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
 {
 	struct gk20a *g = flcn->g;
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gv100.c b/drivers/gpu/nvgpu/common/falcon/falcon_gv100.c
index 801a08975..e907ca0f5 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon_gv100.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon_gv100.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -19,18 +19,14 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#include <nvgpu/falcon.h>
-#include <nvgpu/pmu.h>
 #include <nvgpu/gk20a.h>
 
 #include "falcon_gk20a.h"
 #include "falcon_gp106.h"
 #include "falcon_gv100.h"
+#include "falcon_priv.h"
 #include "gv100/gsp_gv100.h"
 
-#include <nvgpu/hw/gv100/hw_falcon_gv100.h>
-#include <nvgpu/hw/gv100/hw_pgsp_gv100.h>
-
 static void gv100_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
 {
 	struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_priv.h b/drivers/gpu/nvgpu/common/falcon/falcon_priv.h
new file mode 100644
index 000000000..9ce64d2d2
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/falcon/falcon_priv.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FALCON_PRIV_H
+#define NVGPU_FALCON_PRIV_H
+
+#include <nvgpu/lock.h>
+#include <nvgpu/types.h>
+
+/* Falcon Register index */
+#define FALCON_REG_R0		(0U)
+#define FALCON_REG_R1		(1U)
+#define FALCON_REG_R2		(2U)
+#define FALCON_REG_R3		(3U)
+#define FALCON_REG_R4		(4U)
+#define FALCON_REG_R5		(5U)
+#define FALCON_REG_R6		(6U)
+#define FALCON_REG_R7		(7U)
+#define FALCON_REG_R8		(8U)
+#define FALCON_REG_R9		(9U)
+#define FALCON_REG_R10		(10U)
+#define FALCON_REG_R11		(11U)
+#define FALCON_REG_R12		(12U)
+#define FALCON_REG_R13		(13U)
+#define FALCON_REG_R14		(14U)
+#define FALCON_REG_R15		(15U)
+#define FALCON_REG_IV0		(16U)
+#define FALCON_REG_IV1		(17U)
+#define FALCON_REG_UNDEFINED	(18U)
+#define FALCON_REG_EV		(19U)
+#define FALCON_REG_SP		(20U)
+#define FALCON_REG_PC		(21U)
+#define FALCON_REG_IMB		(22U)
+#define FALCON_REG_DMB		(23U)
+#define FALCON_REG_CSW		(24U)
+#define FALCON_REG_CCR		(25U)
+#define FALCON_REG_SEC		(26U)
+#define FALCON_REG_CTX		(27U)
+#define FALCON_REG_EXCI		(28U)
+#define FALCON_REG_RSVD0	(29U)
+#define FALCON_REG_RSVD1	(30U)
+#define FALCON_REG_RSVD2	(31U)
+#define FALCON_REG_SIZE		(32U)
+
+struct gk20a;
+struct nvgpu_falcon;
+struct nvgpu_falcon_queue;
+
+enum falcon_mem_type {
+	MEM_DMEM = 0,
+	MEM_IMEM
+};
+
+struct nvgpu_falcon_queue {
+
+	/* Queue Type (queue_type) */
+	u8 queue_type;
+
+	/* used by nvgpu, for command LPQ/HPQ */
+	struct nvgpu_mutex mutex;
+
+	/* current write position */
+	u32 position;
+	/* physical dmem offset where this queue begins */
+	u32 offset;
+	/* logical queue identifier */
+	u32 id;
+	/* physical queue index */
+	u32 index;
+	/* in bytes */
+	u32 size;
+	/* open-flag */
+	u32 oflag;
+
+	/* queue type(DMEM-Q/FB-Q) specific ops */
+	int (*rewind)(struct nvgpu_falcon *flcn,
+		struct nvgpu_falcon_queue *queue);
+	int (*pop)(struct nvgpu_falcon *flcn,
+		struct nvgpu_falcon_queue *queue, void *data, u32 size,
+		u32 *bytes_read);
+	int (*push)(struct nvgpu_falcon *flcn,
+		struct nvgpu_falcon_queue *queue, void *data, u32 size);
+	bool (*has_room)(struct nvgpu_falcon *flcn,
+		struct nvgpu_falcon_queue *queue, u32 size,
+		bool *need_rewind);
+	int (*tail)(struct nvgpu_falcon *flcn,
+		struct nvgpu_falcon_queue *queue, u32 *tail, bool set);
+	int (*head)(struct nvgpu_falcon *flcn,
+		struct nvgpu_falcon_queue *queue, u32 *head, bool set);
+};
+
+/* ops which are falcon engine specific */
+struct nvgpu_falcon_engine_dependency_ops {
+	int (*reset_eng)(struct gk20a *g);
+	int (*queue_head)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
+		u32 *head, bool set);
+	int (*queue_tail)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
+		u32 *tail, bool set);
+	int (*copy_from_emem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
+		u32 size, u8 port);
+	int (*copy_to_emem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
+		u32 size, u8 port);
+};
+
+struct nvgpu_falcon_ops {
+	int (*reset)(struct nvgpu_falcon *flcn);
+	void (*set_irq)(struct nvgpu_falcon *flcn, bool enable);
+	bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn);
+	bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn);
+	bool (*is_falcon_idle)(struct nvgpu_falcon *flcn);
+	bool (*is_falcon_scrubbing_done)(struct nvgpu_falcon *flcn);
+	int (*copy_from_dmem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
+		u32 size, u8 port);
+	int (*copy_to_dmem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
+		u32 size, u8 port);
+	int (*copy_from_imem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
+		u32 size, u8 port);
+	int (*copy_to_imem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
+		u32 size, u8 port, bool sec, u32 tag);
+	u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index);
+	void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index,
+		u32 data);
+	int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector);
+	void (*dump_falcon_stats)(struct nvgpu_falcon *flcn);
+	int (*bl_bootstrap)(struct nvgpu_falcon *flcn,
+		struct nvgpu_falcon_bl_info *bl_info);
+	void (*get_falcon_ctls)(struct nvgpu_falcon *flcn, u32 *sctl,
+		u32 *cpuctl);
+};
+
+struct nvgpu_falcon {
+	struct gk20a *g;
+	u32 flcn_id;
+	u32 flcn_base;
+	u32 flcn_core_rev;
+	bool is_falcon_supported;
+	bool is_interrupt_enabled;
+	u32 intr_mask;
+	u32 intr_dest;
+	bool isr_enabled;
+	struct nvgpu_mutex isr_mutex;
+	struct nvgpu_mutex copy_lock;
+	struct nvgpu_falcon_ops flcn_ops;
+	struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops;
+};
+
+#endif /* NVGPU_FALCON_PRIV_H */
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_queue.c b/drivers/gpu/nvgpu/common/falcon/falcon_queue.c
index f261faac4..544dd2acc 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon_queue.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon_queue.c
@@ -21,9 +21,9 @@
  */
 
 #include <nvgpu/lock.h>
-#include <nvgpu/timers.h>
 #include <nvgpu/pmu.h>
-#include <nvgpu/falcon.h>
+
+#include "falcon_priv.h"
 
 /* common falcon queue ops */
 static int falcon_queue_head(struct nvgpu_falcon *flcn,
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_tu104.c b/drivers/gpu/nvgpu/common/falcon/falcon_tu104.c
index 57d1bfda2..5be1c69a6 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon_tu104.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon_tu104.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -19,17 +19,14 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#include <nvgpu/falcon.h>
 #include <nvgpu/gk20a.h>
 
 #include "falcon_gk20a.h"
 #include "falcon_gv100.h"
 #include "falcon_tu104.h"
+#include "falcon_priv.h"
 #include "tu104/sec2_tu104.h"
 
-#include <nvgpu/hw/tu104/hw_psec_tu104.h>
-#include <nvgpu/hw/tu104/hw_pnvdec_tu104.h>
-
 static void tu104_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
 {
 	struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c
index c04b172bb..e643c13a4 100644
--- a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c
@@ -44,7 +44,6 @@
 #include "pmu_gm20b.h"
 #include "acr_gm20b.h"
 
-#include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
 
 typedef int (*gm20b_get_ucode_details)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index c281ad4e1..f50794478 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -66,7 +66,6 @@
 #include "common/pmu/pmu_gv11b.h"
 #include "common/pmu/pmu_gv100.h"
 #include "common/falcon/falcon_gk20a.h"
-#include "common/falcon/falcon_gp106.h"
 #include "common/falcon/falcon_gv100.h"
 #include "common/nvdec/nvdec_gp106.h"
 #include "common/nvlink/nvlink_gv100.h"
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
index c78eca3fa..6aced577d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -24,7 +24,6 @@
 #define NVGPU_FALCON_H
 
 #include <nvgpu/types.h>
-#include <nvgpu/lock.h>
 
 /*
  * Falcon Id Defines
@@ -39,41 +38,6 @@
 #define FALCON_ID_END	    (11U)
 #define FALCON_ID_INVALID   0xFFFFFFFFU
 
-/* Falcon Register index */
-#define FALCON_REG_R0		(0U)
-#define FALCON_REG_R1		(1U)
-#define FALCON_REG_R2		(2U)
-#define FALCON_REG_R3		(3U)
-#define FALCON_REG_R4		(4U)
-#define FALCON_REG_R5		(5U)
-#define FALCON_REG_R6		(6U)
-#define FALCON_REG_R7		(7U)
-#define FALCON_REG_R8		(8U)
-#define FALCON_REG_R9		(9U)
-#define FALCON_REG_R10		(10U)
-#define FALCON_REG_R11		(11U)
-#define FALCON_REG_R12		(12U)
-#define FALCON_REG_R13		(13U)
-#define FALCON_REG_R14		(14U)
-#define FALCON_REG_R15		(15U)
-#define FALCON_REG_IV0		(16U)
-#define FALCON_REG_IV1		(17U)
-#define FALCON_REG_UNDEFINED	(18U)
-#define FALCON_REG_EV		(19U)
-#define FALCON_REG_SP		(20U)
-#define FALCON_REG_PC		(21U)
-#define FALCON_REG_IMB		(22U)
-#define FALCON_REG_DMB		(23U)
-#define FALCON_REG_CSW		(24U)
-#define FALCON_REG_CCR		(25U)
-#define FALCON_REG_SEC		(26U)
-#define FALCON_REG_CTX		(27U)
-#define FALCON_REG_EXCI		(28U)
-#define FALCON_REG_RSVD0	(29U)
-#define FALCON_REG_RSVD1	(30U)
-#define FALCON_REG_RSVD2	(31U)
-#define FALCON_REG_SIZE		(32U)
-
 #define FALCON_MAILBOX_0	0x0U
 #define FALCON_MAILBOX_1	0x1U
 #define FALCON_MAILBOX_COUNT 0x02U
@@ -85,11 +49,6 @@
 	(((((ADDR) + (FALCON_BLOCK_SIZE - 1U)) & ~(FALCON_BLOCK_SIZE-1U)) \
 		/ FALCON_BLOCK_SIZE) << 8U)
 
-enum falcon_mem_type {
-	MEM_DMEM = 0,
-	MEM_IMEM
-};
-
 /* Falcon ucode header format
  * OS Code Offset
  * OS Code Size
@@ -117,14 +76,14 @@ enum falcon_mem_type {
 #define APP_0_CODE_OFFSET 0x5U
 #define APP_0_CODE_SIZE   0x6U
 
-struct gk20a;
-struct nvgpu_falcon;
-struct nvgpu_falcon_bl_info;
-
 /* Queue Type */
 #define QUEUE_TYPE_DMEM 0x0U
 #define QUEUE_TYPE_EMEM 0x1U
 
+struct gk20a;
+struct nvgpu_falcon;
+struct nvgpu_falcon_queue;
+
 struct nvgpu_falcon_queue_params {
 	/* Queue Type (queue_type) */
 	u8 queue_type;
@@ -142,83 +101,6 @@ struct nvgpu_falcon_queue_params {
 	u32 oflag;
 };
 
-struct nvgpu_falcon_queue {
-
-	/* Queue Type (queue_type) */
-	u8 queue_type;
-
-	/* used by nvgpu, for command LPQ/HPQ */
-	struct nvgpu_mutex mutex;
-
-	/* current write position */
-	u32 position;
-	/* physical dmem offset where this queue begins */
-	u32 offset;
-	/* logical queue identifier */
-	u32 id;
-	/* physical queue index */
-	u32 index;
-	/* in bytes */
-	u32 size;
-	/* open-flag */
-	u32 oflag;
-
-	/* queue type(DMEM-Q/FB-Q) specific ops */
-	int (*rewind)(struct nvgpu_falcon *flcn,
-		struct nvgpu_falcon_queue *queue);
-	int (*pop)(struct nvgpu_falcon *flcn,
-		struct nvgpu_falcon_queue *queue, void *data, u32 size,
-		u32 *bytes_read);
-	int (*push)(struct nvgpu_falcon *flcn,
-		struct nvgpu_falcon_queue *queue, void *data, u32 size);
-	bool (*has_room)(struct nvgpu_falcon *flcn,
-		struct nvgpu_falcon_queue *queue, u32 size,
-		bool *need_rewind);
-	int (*tail)(struct nvgpu_falcon *flcn,
-		struct nvgpu_falcon_queue *queue, u32 *tail, bool set);
-	int (*head)(struct nvgpu_falcon *flcn,
-		struct nvgpu_falcon_queue *queue, u32 *head, bool set);
-};
-
-/* ops which are falcon engine specific */
-struct nvgpu_falcon_engine_dependency_ops {
-	int (*reset_eng)(struct gk20a *g);
-	int (*queue_head)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
-		u32 *head, bool set);
-	int (*queue_tail)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
-		u32 *tail, bool set);
-	int (*copy_from_emem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
-		u32 size, u8 port);
-	int (*copy_to_emem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
-		u32 size, u8 port);
-};
-
-struct nvgpu_falcon_ops {
-	int (*reset)(struct nvgpu_falcon *flcn);
-	void (*set_irq)(struct nvgpu_falcon *flcn, bool enable);
-	bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn);
-	bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn);
-	bool (*is_falcon_idle)(struct nvgpu_falcon *flcn);
-	bool (*is_falcon_scrubbing_done)(struct nvgpu_falcon *flcn);
-	int (*copy_from_dmem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
-		u32 size, u8 port);
-	int (*copy_to_dmem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
-		u32 size, u8 port);
-	int (*copy_from_imem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
-		u32 size, u8 port);
-	int (*copy_to_imem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
-		u32 size, u8 port, bool sec, u32 tag);
-	u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index);
-	void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index,
-		u32 data);
-	int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector);
-	void (*dump_falcon_stats)(struct nvgpu_falcon *flcn);
-	int (*bl_bootstrap)(struct nvgpu_falcon *flcn,
-		struct nvgpu_falcon_bl_info *bl_info);
-	void (*get_falcon_ctls)(struct nvgpu_falcon *flcn, u32 *sctl,
-		u32 *cpuctl);
-};
-
 struct nvgpu_falcon_bl_info {
 	void *bl_src;
 	u8 *bl_desc;
@@ -227,22 +109,6 @@ struct nvgpu_falcon_bl_info {
 	u32 bl_start_tag;
 };
 
-struct nvgpu_falcon {
-	struct gk20a *g;
-	u32 flcn_id;
-	u32 flcn_base;
-	u32 flcn_core_rev;
-	bool is_falcon_supported;
-	bool is_interrupt_enabled;
-	u32 intr_mask;
-	u32 intr_dest;
-	bool isr_enabled;
-	struct nvgpu_mutex isr_mutex;
-	struct nvgpu_mutex copy_lock;
-	struct nvgpu_falcon_ops flcn_ops;
-	struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops;
-};
-
 int nvgpu_falcon_wait_idle(struct nvgpu_falcon *flcn);
 int nvgpu_falcon_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout);
 int nvgpu_falcon_clear_halt_intr_status(struct nvgpu_falcon *flcn,
diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c
index fce8436c9..96acfed74 100644
--- a/drivers/gpu/nvgpu/tu104/hal_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c
@@ -69,8 +69,6 @@
 #include "common/pmu/acr_gp106.h"
 #include "common/pmu/acr_tu104.h"
 #include "common/falcon/falcon_gk20a.h"
-#include "common/falcon/falcon_gp106.h"
-#include "common/falcon/falcon_gv100.h"
 #include "common/falcon/falcon_tu104.h"
 #include "common/nvdec/nvdec_tu104.h"
 #include "common/top/top_gm20b.h"