diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index e7412caaa..df43c31e9 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -134,12 +134,6 @@ void nvgpu_gr_flush_channel_tlb(struct gk20a *g)
 	nvgpu_spinlock_release(&g->gr.ch_tlb_lock);
 }
 
-u32 nvgpu_gr_get_idle_timeout(struct gk20a *g)
-{
-	return nvgpu_is_timeouts_enabled(g) ?
-		g->poll_timeout_default : UINT_MAX;
-}
-
 int nvgpu_gr_init_fs_state(struct gk20a *g)
 {
 	u32 tpc_index, gpc_index;
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
index 9196bcc8f..581fe20d6 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
@@ -534,7 +534,7 @@ void gm20b_gr_init_cwd_gpcs_tpcs_num(struct gk20a *g,
 
 int gm20b_gr_init_wait_idle(struct gk20a *g)
 {
-	u32 delay = NVGPU_GR_IDLE_CHECK_DEFAULT_US;
+	u32 delay = POLL_DELAY_MIN_US;
 	u32 gr_engine_id;
 	int err = 0;
 	bool ctxsw_active;
@@ -547,7 +547,7 @@ int gm20b_gr_init_wait_idle(struct gk20a *g)
 
 	gr_engine_id = nvgpu_engine_get_gr_id(g);
 
-	err = nvgpu_timeout_init(g, &timeout, nvgpu_gr_get_idle_timeout(g),
+	err = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 				 NVGPU_TIMER_CPU_TIMER);
 	if (err != 0) {
 		return err;
@@ -577,7 +577,7 @@ int gm20b_gr_init_wait_idle(struct gk20a *g)
 		}
 
 		nvgpu_usleep_range(delay, delay * 2U);
-		delay = min_t(u32, delay << 1, NVGPU_GR_IDLE_CHECK_MAX_US);
+		delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
 
 	} while (nvgpu_timeout_expired(&timeout) == 0);
 
@@ -590,7 +590,7 @@ int gm20b_gr_init_wait_idle(struct gk20a *g)
 int gm20b_gr_init_wait_fe_idle(struct gk20a *g)
 {
 	u32 val;
-	u32 delay = NVGPU_GR_IDLE_CHECK_DEFAULT_US;
+	u32 delay = POLL_DELAY_MIN_US;
 	struct nvgpu_timeout timeout;
 	int err = 0;
 
@@ -600,7 +600,7 @@ int gm20b_gr_init_wait_fe_idle(struct gk20a *g)
 
 	nvgpu_log_fn(g, " ");
 
-	err = nvgpu_timeout_init(g, &timeout, nvgpu_gr_get_idle_timeout(g),
+	err = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 				 NVGPU_TIMER_CPU_TIMER);
 	if (err != 0) {
 		return err;
@@ -615,7 +615,7 @@ int gm20b_gr_init_wait_fe_idle(struct gk20a *g)
 		}
 
 		nvgpu_usleep_range(delay, delay * 2U);
-		delay = min_t(u32, delay << 1, NVGPU_GR_IDLE_CHECK_MAX_US);
+		delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
 	} while (nvgpu_timeout_expired(&timeout) == 0);
 
 	nvgpu_err(g, "timeout, fe busy : %x", val);
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
index 143c3879c..c22f31727 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
@@ -146,7 +146,7 @@ static bool gr_activity_empty_or_preempted(u32 val)
 
 int gp10b_gr_init_wait_empty(struct gk20a *g)
 {
-	u32 delay = NVGPU_GR_IDLE_CHECK_DEFAULT_US;
+	u32 delay = POLL_DELAY_MIN_US;
 	bool ctxsw_active;
 	bool gr_busy;
 	u32 gr_status;
@@ -156,7 +156,7 @@ int gp10b_gr_init_wait_empty(struct gk20a *g)
 
 	nvgpu_log_fn(g, " ");
 
-	err = nvgpu_timeout_init(g, &timeout, nvgpu_gr_get_idle_timeout(g),
+	err = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 				 NVGPU_TIMER_CPU_TIMER);
 	if (err != 0) {
 		nvgpu_err(g, "timeout_init failed: %d", err);
@@ -186,7 +186,7 @@ int gp10b_gr_init_wait_empty(struct gk20a *g)
 		}
 
 		nvgpu_usleep_range(delay, delay * 2U);
-		delay = min_t(u32, delay << 1, NVGPU_GR_IDLE_CHECK_MAX_US);
+		delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
 	} while (nvgpu_timeout_expired(&timeout) == 0);
 
 	nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
index 603cc4e22..5bce51439 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
@@ -25,14 +25,10 @@
 
 #include <nvgpu/types.h>
 
-#define NVGPU_GR_IDLE_CHECK_DEFAULT_US		10U
-#define NVGPU_GR_IDLE_CHECK_MAX_US		200U
-
 u32 nvgpu_gr_gpc_offset(struct gk20a *g, u32 gpc);
 u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc);
 int nvgpu_gr_suspend(struct gk20a *g);
 void nvgpu_gr_flush_channel_tlb(struct gk20a *g);
-u32 nvgpu_gr_get_idle_timeout(struct gk20a *g);
 int nvgpu_gr_init_fs_state(struct gk20a *g);
 void nvgpu_gr_wait_initialized(struct gk20a *g);