diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index eb6ee70f7..0705d8b61 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1924,10 +1924,13 @@ static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr)
 
 static u32 get_ecc_override_val(struct gk20a *g)
 {
-	if (tegra_fuse_readl(FUSE_OPT_ECC_EN))
+	u32 val;
+
+	tegra_fuse_readl(FUSE_OPT_ECC_EN, &val);
+	if (val)
 		return gk20a_readl(g, gr_fecs_feature_override_ecc_r());
-	else
-		return 0;
+
+	return 0;
 }
 
 static bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index ec81cf356..c4e44483f 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -190,6 +190,7 @@ int gp10b_init_hal(struct gk20a *g)
 	struct gpu_ops *gops = &g->ops;
 	struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
 	struct gk20a_platform *platform = dev_get_drvdata(g->dev);
+	u32 val;
 
 	*gops = gp10b_ops;
 
@@ -198,8 +199,8 @@ int gp10b_init_hal(struct gk20a *g)
 		gops->privsecurity = 0;
 		gops->securegpccs = 0;
 	} else {
-		if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) &
-				PRIV_SECURITY_ENABLED) {
+		tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val);
+		if (val & PRIV_SECURITY_ENABLED) {
 			gops->privsecurity = 1;
 			gops->securegpccs =1;
 		} else {
@@ -214,8 +215,8 @@ int gp10b_init_hal(struct gk20a *g)
 		gops->privsecurity = 0;
 		gops->securegpccs = 0;
 	} else {
-		if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) &
-				PRIV_SECURITY_ENABLED) {
+		tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val);
+		if (val & PRIV_SECURITY_ENABLED) {
 			gk20a_dbg_info("priv security is not supported but enabled");
 			gops->privsecurity = 1;
 			gops->securegpccs =1;
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index f40c1b7b0..762e2af7e 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -365,9 +365,11 @@ static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask)
 	struct pmu_cmd cmd;
 	u32 seq;
 	int status;
+	u32 val;
 	gk20a_dbg_fn("");
 
-	if (!tegra_fuse_readl(FUSE_OPT_ECC_EN)) {
+	tegra_fuse_readl(FUSE_OPT_ECC_EN, &val);
+	if (!val) {
 		gk20a_err(dev_from_gk20a(g), "Board not ECC capable");
 		return -1;
 	}
@@ -436,12 +438,15 @@ static bool gp10b_is_priv_load(u32 falcon_id)
 /*Dump Security related fuses*/
 static void pmu_dump_security_fuses_gp10b(struct gk20a *g)
 {
+	u32 val;
+
 	gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x",
 			gk20a_readl(g, fuse_opt_sec_debug_en_r()));
 	gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
 			gk20a_readl(g, fuse_opt_priv_sec_en_r()));
+	tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val);
 	gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
-			tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0));
+			val);
 }
 
 void gp10b_init_pmu_ops(struct gpu_ops *gops)