diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
index 8ee146fc5..eef9fd312 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
@@ -1902,10 +1902,10 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
 	int err;
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
 	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
-	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 	struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch);
 	u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE;
 	struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
+	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
 
 	if (tsg == NULL) {
 		return -EINVAL;
@@ -2124,15 +2124,14 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state)
 	u32 no_of_sm;
 	struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
 
-	if((g->ops.gr.init.get_no_of_sm == NULL) ||
-			(g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask == NULL) ||
+	if ((g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask == NULL) ||
 			(g->ops.gr.lock_down_sm == NULL) ||
 			(g->ops.gr.bpt_reg_info == NULL) ||
 			(g->ops.gr.sm_debugger_attached == NULL)) {
 		return -EINVAL;
 	}
 
-	no_of_sm = g->ops.gr.init.get_no_of_sm(g);
+	no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
 
 	if (!g->ops.gr.sm_debugger_attached(g)) {
 		nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c
index baf2a58c0..a85bdcce6 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c
@@ -432,7 +432,7 @@ void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
 	u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0;
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
 	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
-	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
+	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
 
 	/* for maxwell & kepler */
 	u32 numSmPerTpc = 1;
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
index 99ced3670..34a18b976 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
@@ -800,7 +800,7 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
 	u32 gpc, tpc, sm, sm_id;
 	u32 offset;
 	u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0;
-	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
+	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
 
 	for (sm_id = 0; sm_id < no_of_sm; sm_id++) {
 		struct nvgpu_sm_info *sm_info =
@@ -867,11 +867,11 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
 {
 	struct nvgpu_dbg_reg_op *ops;
 	unsigned int i = 0, sm_id;
-	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 	int err;
 	struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch);
 	u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE;
 	struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
+	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
 
 	if (tsg == NULL) {
 		nvgpu_err(g, "gv11b_gr_set_sm_debug_mode failed=>tsg NULL");
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
index 52e20859f..220ba2236 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
@@ -759,7 +759,7 @@ int gv11b_gr_init_commit_sm_id_programming(struct gk20a *g,
 	u32 *tpc_sm_id;
 	u32 sm_id_size = g->ops.gr.init.get_sm_id_size();
 
-	for (sm_id = 0; sm_id < g->ops.gr.init.get_no_of_sm(g);
+	for (sm_id = 0; sm_id < nvgpu_gr_config_get_no_of_sm(config);
 			sm_id++) {
 		struct nvgpu_sm_info *sm_info =
 			((gr_ctx == NULL) ||
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index 92a636ec4..257b54ceb 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -855,8 +855,10 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
 	struct warpstate *ioctl_w_state;
 	struct nvgpu_warpstate *w_state = NULL;
 	u32 ioctl_size, size, sm_id, no_of_sm;
+	struct nvgpu_gr_config *gr_config =
+		nvgpu_gr_get_gr_instance_config_ptr(g, gr_instance_id);
 
-	no_of_sm = g->ops.gr.init.get_no_of_sm(g);
+	no_of_sm = nvgpu_gr_config_get_no_of_sm(gr_config);
 
 	ioctl_size = no_of_sm * sizeof(struct warpstate);
 	ioctl_w_state = nvgpu_kzalloc(g, ioctl_size);