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gpu: nvgpu: unit: init: update to work with new init design
To address CCM in nvgpu_finalize_poweron(), some init APIs were updated and broke the init unit test, so it was disabled. This addresses the breakage and re-enables the test. JIRA NVGPU-3980 Change-Id: I61b6595e0903373c36f949a5ec1e85718fd13f32 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2207420 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
Alex Waterman
parent
d10447e717
commit
4a5ee02291
@@ -107,29 +107,6 @@ static int falcon_sw_init(struct gk20a *g, u32 falcon_id)
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return 0;
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return 0;
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}
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}
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/* pmu_early_init is passed a unique struct */
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struct nvgpu_pmu;
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static int pmu_early_init_return = 0;
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static int pmu_early_init(struct gk20a *g, struct nvgpu_pmu **pmu)
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{
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return pmu_early_init_return;
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}
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/* acr_init is passed a unique struct */
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struct nvgpu_acr;
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static int acr_init_return = 0;
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static int acr_init(struct gk20a *g, struct nvgpu_acr **acr)
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{
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return acr_init_return;
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}
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/* acr_construct_execute is passed a unique struct */
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static int acr_construct_execute_return = 0;
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static int acr_construct_execute(struct gk20a *g, struct nvgpu_acr *acr)
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{
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return acr_construct_execute_return;
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}
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/* generic for passing in a u32 */
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/* generic for passing in a u32 */
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static int return_success_u32_param(struct gk20a *g, u32 dummy)
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static int return_success_u32_param(struct gk20a *g, u32 dummy)
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{
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{
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@@ -372,25 +349,20 @@ static void set_poweron_funcs_success(struct gk20a *g)
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setup_simple_init_func_success(&g->ops.gr.ecc.ecc_init_support, i++);
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setup_simple_init_func_success(&g->ops.gr.ecc.ecc_init_support, i++);
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setup_simple_init_func_success(&g->ops.therm.init_therm_support, i++);
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setup_simple_init_func_success(&g->ops.therm.init_therm_support, i++);
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setup_simple_init_func_success(&g->ops.ce.ce_init_support, i++);
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setup_simple_init_func_success(&g->ops.ce.ce_init_support, i++);
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setup_simple_init_func_success(&g->ops.bus.init_hw, i++);
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setup_simple_init_func_success(&g->ops.priv_ring.enable_priv_ring, i++);
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setup_simple_init_func_success(&g->ops.mc.intr_enable, i++);
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setup_simple_init_func_success(&g->ops.channel.resume_all_serviceable_ch, i++);
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setup_simple_init_func_success(&g->ops.pmu.pmu_early_init, i++);
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setup_simple_init_func_success(&g->ops.acr.acr_init, i++);
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setup_simple_init_func_success(&g->ops.acr.acr_construct_execute, i++);
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simple_init_func_ptrs_count = i;
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simple_init_func_ptrs_count = i;
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/* these don't even return anything */
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g->ops.bus.init_hw = no_return;
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g->ops.priv_ring.enable_priv_ring = no_return;
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g->ops.mc.intr_enable = no_return;
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g->ops.channel.resume_all_serviceable_ch = no_return;
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/* these are the exceptions */
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/* these are the exceptions */
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g->ops.falcon.falcon_sw_init = falcon_sw_init;
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g->ops.falcon.falcon_sw_init = falcon_sw_init;
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falcon_fail_on_id = U32_MAX; /* don't fail */
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falcon_fail_on_id = U32_MAX; /* don't fail */
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g->ops.pmu.pmu_early_init = pmu_early_init;
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pmu_early_init_return = 0;
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g->ops.acr.acr_init = acr_init;
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acr_init_return = 0;
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g->ops.fuse.fuse_status_opt_tpc_gpc = return_u32_u32_param;
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g->ops.fuse.fuse_status_opt_tpc_gpc = return_u32_u32_param;
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g->ops.tpc.tpc_powergate = return_success_u32_param;
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g->ops.tpc.tpc_powergate = return_success_u32_param;
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g->ops.acr.acr_construct_execute = acr_construct_execute;
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acr_construct_execute_return = 0;
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g->ops.falcon.falcon_sw_free = no_return_u32_param;
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g->ops.falcon.falcon_sw_free = no_return_u32_param;
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/* used in support functions */
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/* used in support functions */
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@@ -422,7 +394,8 @@ int test_poweron(struct unit_module *m, struct gk20a *g, void *args)
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err = nvgpu_finalize_poweron(g);
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err = nvgpu_finalize_poweron(g);
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if (err == 0) {
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if (err == 0) {
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unit_return_fail(m,
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unit_return_fail(m,
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"nvgpu_finalize_poweron errantly returned success\n");
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"nvgpu_finalize_poweron errantly returned success i=%d\n",
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i);
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}
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}
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*simple_init_func_ptrs[i] = return_success;
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*simple_init_func_ptrs[i] = return_success;
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}
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}
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@@ -446,25 +419,6 @@ int test_poweron(struct unit_module *m, struct gk20a *g, void *args)
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}
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}
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falcon_fail_on_id = U32_MAX; /* stop failing */
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falcon_fail_on_id = U32_MAX; /* stop failing */
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pmu_early_init_return = -1;
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g->power_on = false;
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err = nvgpu_finalize_poweron(g);
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if (err == 0) {
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unit_return_fail(m,
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"nvgpu_finalize_poweron errantly returned success\n");
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}
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pmu_early_init_return = 0;
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acr_init_return = -1;
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g->power_on = false;
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err = nvgpu_finalize_poweron(g);
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if (err == 0) {
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unit_return_fail(m,
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"nvgpu_finalize_poweron errantly returned success\n");
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}
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acr_init_return = 0;
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g->ops.tpc.tpc_powergate = return_failure_u32_param;
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g->ops.tpc.tpc_powergate = return_failure_u32_param;
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g->power_on = false;
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g->power_on = false;
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err = nvgpu_finalize_poweron(g);
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err = nvgpu_finalize_poweron(g);
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@@ -474,15 +428,6 @@ int test_poweron(struct unit_module *m, struct gk20a *g, void *args)
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}
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}
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g->ops.tpc.tpc_powergate = return_success_u32_param;
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g->ops.tpc.tpc_powergate = return_success_u32_param;
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acr_construct_execute_return = -1;
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g->power_on = false;
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err = nvgpu_finalize_poweron(g);
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if (err == 0) {
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unit_return_fail(m,
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"nvgpu_finalize_poweron errantly returned success\n");
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}
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acr_construct_execute_return = 0;
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/* test the case of already being powered on */
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/* test the case of already being powered on */
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g->power_on = true;
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g->power_on = true;
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err = nvgpu_finalize_poweron(g);
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err = nvgpu_finalize_poweron(g);
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