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gpu: nvgpu: chip specific channel commit_inst

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Add function pointer to add chip specific commit_inst.
Update this function pointer for gk20a and gm20b.

JIRA GV11B-21

Change-Id: Iae7231fae70c7b4f56647fe242776670675de3fd
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1258275
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2016-11-22 10:46:55 -08:00
committed by mobile promotions
parent af5d2d208a
commit 4a8802eab4
4 changed files with 10 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -312,6 +312,7 @@ struct gpu_ops {
u32 zcull_alloc_num, u32 *zcull_map_tiles); u32 zcull_alloc_num, u32 *zcull_map_tiles);
int (*commit_global_timeslice)(struct gk20a *g, int (*commit_global_timeslice)(struct gk20a *g,
struct channel_gk20a *c, bool patch); struct channel_gk20a *c, bool patch);
int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va);
} gr; } gr;
const char *name; const char *name;
struct { struct {

12
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -75,7 +75,6 @@
#define FECS_ARB_CMD_TIMEOUT_DEFAULT 2 #define FECS_ARB_CMD_TIMEOUT_DEFAULT 2
static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g); static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g);
static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va);
/* global ctx buffer */ /* global ctx buffer */
static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g); static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g);
@@ -633,7 +632,7 @@ int gr_gk20a_halt_pipe(struct gk20a *g)
} }
static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va) int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va)
{ {
u32 addr_lo; u32 addr_lo;
u32 addr_hi; u32 addr_hi;
@@ -1690,7 +1689,7 @@ restore_fe_go_idle:
gk20a_mem_wr(g, gold_mem, ctxsw_prog_main_image_zcull_ptr_o(), 0); gk20a_mem_wr(g, gold_mem, ctxsw_prog_main_image_zcull_ptr_o(), 0);
gr_gk20a_commit_inst(c, ch_ctx->global_ctx_buffer_va[GOLDEN_CTX_VA]); g->ops.gr.commit_inst(c, ch_ctx->global_ctx_buffer_va[GOLDEN_CTX_VA]);
gr_gk20a_fecs_ctx_image_save(c, gr_fecs_method_push_adr_wfi_golden_save_v()); gr_gk20a_fecs_ctx_image_save(c, gr_fecs_method_push_adr_wfi_golden_save_v());
@@ -1709,7 +1708,7 @@ restore_fe_go_idle:
gr->ctx_vars.golden_image_size); gr->ctx_vars.golden_image_size);
} }
gr_gk20a_commit_inst(c, gr_mem->gpu_va); g->ops.gr.commit_inst(c, gr_mem->gpu_va);
gr->ctx_vars.golden_image_initialized = true; gr->ctx_vars.golden_image_initialized = true;
@@ -2063,7 +2062,7 @@ static int gr_gk20a_init_ctxsw_ucode_vaspace(struct gk20a *g)
if (err) if (err)
return err; return err;
gk20a_init_inst_block(&ucode_info->inst_blk_desc, vm, 0); g->ops.mm.init_inst_block(&ucode_info->inst_blk_desc, vm, 0);
/* Map ucode surface to GMMU */ /* Map ucode surface to GMMU */
ucode_info->surface_desc.gpu_va = gk20a_gmmu_map(vm, ucode_info->surface_desc.gpu_va = gk20a_gmmu_map(vm,
@@ -3050,7 +3049,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c,
ch_ctx->pm_ctx.pm_mode = ctxsw_prog_main_image_pm_mode_no_ctxsw_f(); ch_ctx->pm_ctx.pm_mode = ctxsw_prog_main_image_pm_mode_no_ctxsw_f();
/* commit gr ctx buffer */ /* commit gr ctx buffer */
err = gr_gk20a_commit_inst(c, ch_ctx->gr_ctx->mem.gpu_va); err = g->ops.gr.commit_inst(c, ch_ctx->gr_ctx->mem.gpu_va);
if (err) { if (err) {
gk20a_err(dev_from_gk20a(g), gk20a_err(dev_from_gk20a(g),
"fail to commit gr ctx buffer"); "fail to commit gr ctx buffer");
@@ -9128,4 +9127,5 @@ void gk20a_init_gr_ops(struct gpu_ops *gops)
gops->gr.setup_rop_mapping = gr_gk20a_setup_rop_mapping; gops->gr.setup_rop_mapping = gr_gk20a_setup_rop_mapping;
gops->gr.program_zcull_mapping = gr_gk20a_program_zcull_mapping; gops->gr.program_zcull_mapping = gr_gk20a_program_zcull_mapping;
gops->gr.commit_global_timeslice = gr_gk20a_commit_global_timeslice; gops->gr.commit_global_timeslice = gr_gk20a_commit_global_timeslice;
gops->gr.commit_inst = gr_gk20a_commit_inst;
} }

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
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@@ -667,6 +667,8 @@ int gr_gk20a_commit_global_timeslice(struct gk20a *g,
void gr_gk20a_init_sm_id_table(struct gk20a *g); void gr_gk20a_init_sm_id_table(struct gk20a *g);
int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va);
static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode)
{ {
switch (graphics_preempt_mode) { switch (graphics_preempt_mode) {

1
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
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@@ -1589,4 +1589,5 @@ void gm20b_init_gr(struct gpu_ops *gops)
gops->gr.setup_rop_mapping = gr_gk20a_setup_rop_mapping; gops->gr.setup_rop_mapping = gr_gk20a_setup_rop_mapping;
gops->gr.program_zcull_mapping = gr_gk20a_program_zcull_mapping; gops->gr.program_zcull_mapping = gr_gk20a_program_zcull_mapping;
gops->gr.commit_global_timeslice = gr_gk20a_commit_global_timeslice; gops->gr.commit_global_timeslice = gr_gk20a_commit_global_timeslice;
gops->gr.commit_inst = gr_gk20a_commit_inst;
} }