gpu: nvgpu: Move ELCG programming to therm

Implement gp10b and gp106 ELCG programming.

JIRA DNVGPU-74

Change-Id: Ic0349b948a2870e0d39e95ddd2f49231e7b4cbe0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1220431
(cherry picked from commit d6bc48647982babdf642ea6004d4208c5daa243f)
Reviewed-on: http://git-master/r/1239422
GVS: Gerrit_Virtual_Submit

drivers/gpu/nvgpu/gp106/hw_therm_gp106.h

@@ -94,4 +94,84 @@ static inline u32 therm_temp_sensor_tsense_state_shadow_v(void)
 {
 	return 0x00000002;
 }
+static inline u32 therm_gate_ctrl_r(u32 i)
+{
+	return 0x00020200 + i*4;
+}
+static inline u32 therm_gate_ctrl_eng_clk_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
+{
+	return 0x0;
+}
+static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
+{
+	return 0x1;
+}
+static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
+{
+	return 0x2;
+}
+static inline u32 therm_gate_ctrl_blk_clk_m(void)
+{
+	return 0x3 << 2;
+}
+static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
+{
+	return 0x0;
+}
+static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
+{
+	return 0x4;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
+{
+	return (v & 0x1f) << 8;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
+{
+	return 0x1f << 8;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
+{
+	return (v & 0x7) << 13;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
+{
+	return 0x7 << 13;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
+{
+	return (v & 0xf) << 16;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
+{
+	return 0xf << 16;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
+{
+	return (v & 0xf) << 20;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
+{
+	return 0xf << 20;
+}
+static inline u32 therm_fecs_idle_filter_r(void)
+{
+	return 0x00020288;
+}
+static inline u32 therm_fecs_idle_filter_value_m(void)
+{
+	return 0xffffffff << 0;
+}
+static inline u32 therm_hubmmu_idle_filter_r(void)
+{
+	return 0x0002028c;
+}
+static inline u32 therm_hubmmu_idle_filter_value_m(void)
+{
+	return 0xffffffff << 0;
+}
 #endif

drivers/gpu/nvgpu/gp106/therm_gp106.c

@@ -55,8 +55,53 @@ static void gp106_therm_debugfs_init(struct gk20a *g) {
 }
 #endif
 
+static int gp106_elcg_init_idle_filters(struct gk20a *g)
+{
+	u32 gate_ctrl, idle_filter;
+	u32 engine_id;
+	u32 active_engine_id = 0;
+	struct fifo_gk20a *f = &g->fifo;
+
+	gk20a_dbg_fn("");
+
+	for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
+		active_engine_id = f->active_engines_list[engine_id];
+		gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
+
+		if (tegra_platform_is_linsim()) {
+			gate_ctrl = set_field(gate_ctrl,
+				therm_gate_ctrl_eng_delay_after_m(),
+				therm_gate_ctrl_eng_delay_after_f(4));
+		}
+
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_idle_filt_exp_m(),
+			therm_gate_ctrl_eng_idle_filt_exp_f(2));
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_idle_filt_mant_m(),
+			therm_gate_ctrl_eng_idle_filt_mant_f(1));
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_delay_before_m(),
+			therm_gate_ctrl_eng_delay_before_f(0));
+		gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
+	}
+
+	/* default fecs_idle_filter to 0 */
+	idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
+	idle_filter &= ~therm_fecs_idle_filter_value_m();
+	gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
+	/* default hubmmu_idle_filter to 0 */
+	idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
+	idle_filter &= ~therm_hubmmu_idle_filter_value_m();
+	gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
+
+	gk20a_dbg_fn("done");
+	return 0;
+}
+
 void gp106_init_therm_ops(struct gpu_ops *gops) {
 #ifdef CONFIG_DEBUG_FS
 	gops->therm.therm_debugfs_init = gp106_therm_debugfs_init;
 #endif
+	gops->therm.elcg_init_idle_filters = gp106_elcg_init_idle_filters;
 }

drivers/gpu/nvgpu/gp10b/therm_gp10b.c

@@ -78,28 +78,53 @@ static int gp10b_init_therm_setup_hw(struct gk20a *g)
 	return 0;
 }
 
-static int gp10b_update_therm_gate_ctrl(struct gk20a *g)
+static int gp10b_elcg_init_idle_filters(struct gk20a *g)
 {
-	u32 gate_ctrl;
+	u32 gate_ctrl, idle_filter;
 	u32 engine_id;
 	u32 active_engine_id = 0;
 	struct fifo_gk20a *f = &g->fifo;
 
+	gk20a_dbg_fn("");
+
 	for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
 		active_engine_id = f->active_engines_list[engine_id];
 		gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
+
+		if (tegra_platform_is_linsim()) {
+			gate_ctrl = set_field(gate_ctrl,
+				therm_gate_ctrl_eng_delay_after_m(),
+				therm_gate_ctrl_eng_delay_after_f(4));
+		}
+
+		/* 2 * (1 << 9) = 1024 clks */
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_idle_filt_exp_m(),
+			therm_gate_ctrl_eng_idle_filt_exp_f(9));
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_idle_filt_mant_m(),
+			therm_gate_ctrl_eng_idle_filt_mant_f(2));
 		gate_ctrl = set_field(gate_ctrl,
 			therm_gate_ctrl_eng_delay_before_m(),
 			therm_gate_ctrl_eng_delay_before_f(4));
 		gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
 	}
 
+	/* default fecs_idle_filter to 0 */
+	idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
+	idle_filter &= ~therm_fecs_idle_filter_value_m();
+	gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
+	/* default hubmmu_idle_filter to 0 */
+	idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
+	idle_filter &= ~therm_hubmmu_idle_filter_value_m();
+	gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
+
+	gk20a_dbg_fn("done");
 	return 0;
 }
 
 void gp10b_init_therm_ops(struct gpu_ops *gops)
 {
 	gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw;
-	gops->therm.update_therm_gate_ctrl = gp10b_update_therm_gate_ctrl;
+	gops->therm.elcg_init_idle_filters = gp10b_elcg_init_idle_filters;
-
 }