diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk index c22e79375..a280031e4 100644 --- a/Makefile.umbrella.tmk +++ b/Makefile.umbrella.tmk @@ -73,6 +73,7 @@ NV_REPOSITORY_COMPONENTS += userspace/units/falcon/falcon_tests NV_REPOSITORY_COMPONENTS += userspace/units/pmu NV_REPOSITORY_COMPONENTS += userspace/units/gr NV_REPOSITORY_COMPONENTS += userspace/units/gr/config +NV_REPOSITORY_COMPONENTS += userspace/units/gr/init endif # Local Variables: diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export index 8a9e545c7..16fd95399 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export @@ -212,6 +212,7 @@ nvgpu_posix_io_register_reg_space nvgpu_posix_io_start_recorder nvgpu_posix_io_unregister_reg_space nvgpu_posix_io_writel_reg_space +nvgpu_posix_io_get_reg_space nvgpu_posix_is_fault_injection_triggered nvgpu_posix_probe nvgpu_posix_register_io diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index 47f348773..6673d1c4b 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -73,11 +73,12 @@ UNITS := \ $(UNIT_SRC)/fifo/tsg \ $(UNIT_SRC)/list \ $(UNIT_SRC)/enabled \ - $(UNIT_SRC)/gr \ - $(UNIT_SRC)/gr/config \ $(UNIT_SRC)/falcon \ $(UNIT_SRC)/falcon/falcon_tests \ - $(UNIT_SRC)/pmu + $(UNIT_SRC)/pmu \ + $(UNIT_SRC)/gr \ + $(UNIT_SRC)/gr/config \ + $(UNIT_SRC)/gr/init ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1) UNITS += $(UNIT_SRC)/fuse diff --git a/userspace/required_tests.json b/userspace/required_tests.json index 77750908a..5e87327e1 100644 --- a/userspace/required_tests.json +++ b/userspace/required_tests.json @@ -1402,5 +1402,20 @@ "test": "remove_support", "test_level": 0, "unit": "nvgpu_gr_config" + }, + { + "test": "init_support", + "test_level": 0, + "unit": "nvgpu_gr_init" + }, + { + "test": "init_prepare", + "test_level": 0, + "unit": "nvgpu_gr_init" + }, + { + "test": "remove_support", + "test_level": 0, + "unit": "nvgpu_gr_init" } ] diff --git a/userspace/units/gr/config/nvgpu-gr-config.c b/userspace/units/gr/config/nvgpu-gr-config.c index ffcae8010..f9f5528c4 100644 --- a/userspace/units/gr/config/nvgpu-gr-config.c +++ b/userspace/units/gr/config/nvgpu-gr-config.c @@ -291,7 +291,6 @@ set_get_fail: struct unit_module_test nvgpu_gr_config_tests[] = { UNIT_TEST(init_support, test_gr_init_support, NULL, 0), - UNIT_TEST(init_prepare, test_gr_init_prepare, NULL, 0), UNIT_TEST(config_init, test_gr_config_init, NULL, 0), UNIT_TEST(config_check_init, test_gr_config_count, NULL, 0), UNIT_TEST(config_check_set_get, test_gr_config_set_get, NULL, 0), diff --git a/userspace/units/gr/init/Makefile b/userspace/units/gr/init/Makefile new file mode 100644 index 000000000..060c352ea --- /dev/null +++ b/userspace/units/gr/init/Makefile @@ -0,0 +1,33 @@ +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = nvgpu-gr-init.o +MODULE = nvgpu-gr-init + +LIB_PATHS += -lnvgpu-gr +include ../../Makefile.units + +lib$(MODULE).so: nvgpu-gr + +nvgpu-gr: + $(MAKE) -C .. + diff --git a/userspace/units/gr/init/Makefile.interface.tmk b/userspace/units/gr/init/Makefile.interface.tmk new file mode 100644 index 000000000..a7a204f46 --- /dev/null +++ b/userspace/units/gr/init/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=nvgpu-gr-init + +include $(NV_COMPONENT_DIR)/../../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/gr/init/Makefile.tmk b/userspace/units/gr/init/Makefile.tmk new file mode 100644 index 000000000..21366ed6d --- /dev/null +++ b/userspace/units/gr/init/Makefile.tmk @@ -0,0 +1,40 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME = nvgpu-gr-init +NVGPU_UNIT_SRCS = nvgpu-gr-init.c + +NVGPU_UNIT_INTERFACE_DIRS := \ + $(NV_COMPONENT_DIR)/.. \ + $(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu + +include $(NV_COMPONENT_DIR)/../../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/gr/init/nvgpu-gr-init.c b/userspace/units/gr/init/nvgpu-gr-init.c new file mode 100644 index 000000000..358e79906 --- /dev/null +++ b/userspace/units/gr/init/nvgpu-gr-init.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include + +#include +#include + +#include +#include +#include + +#include "common/gr/gr_priv.h" + +#include "../nvgpu-gr.h" + +struct unit_module_test nvgpu_gr_init_tests[] = { + UNIT_TEST(init_support, test_gr_init_support, NULL, 0), + UNIT_TEST(init_prepare, test_gr_init_prepare, NULL, 0), + UNIT_TEST(remove_support, test_gr_remove_support, NULL, 0), +}; + +UNIT_MODULE(nvgpu_gr_init, nvgpu_gr_init_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/gr/nvgpu-gr-gv11b-regs.h b/userspace/units/gr/nvgpu-gr-gv11b-regs.h index d06ac1f40..5dcf6ff49 100644 --- a/userspace/units/gr/nvgpu-gr-gv11b-regs.h +++ b/userspace/units/gr/nvgpu-gr-gv11b-regs.h @@ -32,20 +32,15 @@ #include -u32 gv11b_priv_ring_regs[] = { +u32 gr_gv11b_priv_ring_regs[] = { +/* 0x00120060 */ 0x00000000, 0x00000cd7, 0xbadf5040, 0x00000000, /* 0x00120070 */ 0x00000001, 0x00000001, 0x00000001, 0x00000000, /* 0x00120080 */ 0x00010a00, 0x00162648, 0x020080c2, 0x4081e088, /* 0x00120090 */ 0x01040842, 0xbadf5040, 0x00000000, 0x00000000, /* 0x001200a0 */ 0x0000008f, 0x0000008f, 0x00000001, 0x00000001, }; -struct nvgpu_posix_io_reg_space gv11b_priv_ring_reg_space = { - .base = 0x00120070, - .size = sizeof(gv11b_priv_ring_regs), - .data = gv11b_priv_ring_regs, -}; - -u32 gv11b_master_regs[] = { +u32 gr_gv11b_master_regs[] = { /* 0x00000000 */ 0x15b000a1, 0x00000000, 0x00000000, 0xbadf5040, /* 0x00000010 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040, /* 0x00000020 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040, @@ -304,13 +299,7 @@ u32 gv11b_master_regs[] = { /* 0x00000ff0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040, }; -struct nvgpu_posix_io_reg_space gv11b_master_reg_space = { - .base = 0x00000000, - .size = sizeof(gv11b_master_regs), - .data = gv11b_master_regs, -}; - -u32 gv11b_fuse_regs[] = { +u32 gr_gv11b_fuse_regs[] = { /* 0x00021000 */ 0x000000ff, 0xbadf5040, 0xbadf5040, 0xbadf5040, /* 0x00021010 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040, /* 0x00021020 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040, @@ -569,13 +558,7 @@ u32 gv11b_fuse_regs[] = { /* 0x00021ff0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040, }; -struct nvgpu_posix_io_reg_space gv11b_fuse_reg_space = { - .base = 0x00021000, - .size = sizeof(gv11b_fuse_regs), - .data = gv11b_fuse_regs, -}; - -u32 gv11b_top_regs[] = { +u32 gr_gv11b_top_regs[] = { /* 0x00022400 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, /* 0x00022410 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0x00000081, /* 0x00022420 */ 0x04444924, 0x00000010, 0xbadf5040, 0xbadf5040, @@ -642,13 +625,7 @@ u32 gv11b_top_regs[] = { /* 0x000227f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; -struct nvgpu_posix_io_reg_space gv11b_top_reg_space = { - .base = 0x22400, - .size = sizeof(gv11b_top_regs), - .data = gv11b_top_regs, -}; - -u32 gv11b_gr_regs[] = { +u32 gr_gv11b_gr_regs[] = { /* 0x00400080 */ 0x00300bd2, 0x00000000, 0xf607bfe7, 0x00060000, /* 0x00400090 */ 0x00000030, 0xbadf5040, 0xbadf5040, 0xbadf5040, /* 0x004000a0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040, @@ -3251,37 +3228,58 @@ u32 gv11b_gr_regs[] = { /* 0x0040a2f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; -struct nvgpu_posix_io_reg_space gv11b_gr_reg_space = { - .base = 0x00400080, - .size = sizeof(gv11b_gr_regs), - .data = gv11b_gr_regs, -}; - /* * GR pes_tpc_mask registers */ -u32 gv11b_gr_pes_tpc_mask_regs[] = { +u32 gr_gv11b_pes_tpc_mask_regs[] = { /* 0x00500c30 */ 0x00000005, 0x0000000a, 0x00000000, 0x00000000, }; -struct nvgpu_posix_io_reg_space gv11b_gr_pes_tpc_mask_reg_space = { - .base = 0x00500c30, - .size = sizeof(gv11b_gr_pes_tpc_mask_regs), - .data = gv11b_gr_pes_tpc_mask_regs, -}; - /* * GR floor sweeping registers */ -u32 gv11b_gr_fs_regs[] = { +u32 gr_gv11b_fs_regs[] = { /* 0x00502604 */ 0x02010001, 0x00040004, 0x00000000, 0x00000000, /* 0x00502614 */ 0x00000a20, 0x00000000, 0x00000000, 0x00001440, }; -struct nvgpu_posix_io_reg_space gv11b_gr_fs_reg_space = { - .base = 0x00502604, - .size = sizeof(gv11b_gr_fs_regs), - .data = gv11b_gr_fs_regs, +#define gr_array_reg_space(x) sizeof(x)/sizeof(struct nvgpu_posix_io_reg_space) +struct nvgpu_posix_io_reg_space gr_gv11b_initialized_reg_space[] = { + [0] = { + .base = 0x00120060, + .size = sizeof(gr_gv11b_priv_ring_regs), + .data = gr_gv11b_priv_ring_regs, + }, + [1] = { + .base = 0x00000000, + .size = sizeof(gr_gv11b_master_regs), + .data = gr_gv11b_master_regs, + }, + [2] = { + .base = 0x00021000, + .size = sizeof(gr_gv11b_fuse_regs), + .data = gr_gv11b_fuse_regs, + }, + [3] = { + .base = 0x00022400, + .size = sizeof(gr_gv11b_top_regs), + .data = gr_gv11b_top_regs, + }, + [4] = { + .base = 0x00400080, + .size = sizeof(gr_gv11b_gr_regs), + .data = gr_gv11b_gr_regs, + }, + [5] = { + .base = 0x00500c30, + .size = sizeof(gr_gv11b_pes_tpc_mask_regs), + .data = gr_gv11b_pes_tpc_mask_regs, + }, + [6] = { + .base = 0x00502604, + .size = sizeof(gr_gv11b_fs_regs), + .data = gr_gv11b_fs_regs, + }, }; #endif /* UNIT_NVGPU_GR_GV11B_REGS_H */ diff --git a/userspace/units/gr/nvgpu-gr-gv11b.c b/userspace/units/gr/nvgpu-gr-gv11b.c index 66c762962..7ca769c28 100644 --- a/userspace/units/gr/nvgpu-gr-gv11b.c +++ b/userspace/units/gr/nvgpu-gr-gv11b.c @@ -86,54 +86,67 @@ static struct nvgpu_posix_io_callbacks gr_test_reg_callbacks = { .tegra_fuse_readl = tegra_fuse_readl_access_reg_fn, }; +static void gr_io_delete_initialized_reg_space(struct unit_module *m, struct gk20a *g) +{ + u32 i = 0; + u32 arr_size = gr_array_reg_space(gr_gv11b_initialized_reg_space); + + for (i = 0; i < arr_size; i++) { + u32 base = gr_gv11b_initialized_reg_space[i].base; + + nvgpu_posix_io_delete_reg_space(g, base); + } +} + +static int gr_io_add_initialized_reg_space(struct unit_module *m, struct gk20a *g) +{ + int ret = UNIT_SUCCESS; + u32 arr_size = gr_array_reg_space(gr_gv11b_initialized_reg_space); + u32 i = 0, j = 0; + u32 base, size; + struct nvgpu_posix_io_reg_space *gr_io_reg; + + for (i = 0; i < arr_size; i++) { + base = gr_gv11b_initialized_reg_space[i].base; + size = gr_gv11b_initialized_reg_space[i].size; + + if (nvgpu_posix_io_add_reg_space(g, base, size) != 0) { + unit_err(m, "failed to add reg space for %08x\n", base); + ret = UNIT_FAIL; + goto clean_init_reg_space; + } + + gr_io_reg = nvgpu_posix_io_get_reg_space(g, base); + if (gr_io_reg == NULL) { + unit_err(m, "failed to get reg space for %08x\n", base); + ret = UNIT_FAIL; + goto clean_init_reg_space; + } + + memcpy(gr_io_reg->data, gr_gv11b_initialized_reg_space[i].data, size); + } + + return ret; + +clean_init_reg_space: + for (j = 0; j < i; j++) { + base = gr_gv11b_initialized_reg_space[j].base; + nvgpu_posix_io_delete_reg_space(g, base); + } + + return ret; +} + int test_gr_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g) { /* Create register space */ nvgpu_posix_io_init_reg_space(g); - if (nvgpu_posix_io_register_reg_space(g, - &gv11b_master_reg_space) != 0) { - unit_err(m, "%s: failed to create master register space\n", - __func__); + if (gr_io_add_initialized_reg_space(m, g) == UNIT_FAIL) { + unit_err(m, "failed to get initialized reg space\n"); return UNIT_FAIL; } - if (nvgpu_posix_io_register_reg_space(g, &gv11b_top_reg_space) != 0) { - unit_err(m, "%s: failed to create top register space\n", - __func__); - goto clean_up_master; - } - - if (nvgpu_posix_io_register_reg_space(g, &gv11b_fuse_reg_space) != 0) { - unit_err(m, "%s: failed to create fuse register space\n", - __func__); - goto clean_up_top; - } - - if (nvgpu_posix_io_register_reg_space(g, &gv11b_gr_reg_space) != 0) { - unit_err(m, "%s: failed to create gr register space\n", - __func__); - goto clean_up_fuse; - } - - if (nvgpu_posix_io_register_reg_space(g, &gv11b_priv_ring_reg_space) != 0) { - unit_err(m, "%s: failed to create priv_ring register space\n", - __func__); - goto clean_up_gr; - } - - if (nvgpu_posix_io_register_reg_space(g, &gv11b_gr_pes_tpc_mask_reg_space) != 0) { - unit_err(m, "%s: failed to create gr pes_tpc_mask register space\n", - __func__); - goto clean_up_priv_ring; - } - - if (nvgpu_posix_io_register_reg_space(g, &gv11b_gr_fs_reg_space) != 0) { - unit_err(m, "%s: failed to create gr floorsweep register space\n", - __func__); - goto clean_up_pes_tpc_mask; - } - /* * GPCS_SWDX reg space * @@ -141,7 +154,7 @@ int test_gr_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g) if (nvgpu_posix_io_add_reg_space(g, gr_gpcs_swdx_dss_zbc_color_r_r(0), 0xEFF) != 0) { unit_err(m, "Add gpcs swdx reg space failed!\n"); - goto clean_up_fs_space; + goto clean_up_reg_space; } /* @@ -208,20 +221,7 @@ clean_up_gcc_space: nvgpu_posix_io_delete_reg_space(g, gr_pri_gpcs_gcc_dbg_r()); clean_up_swdx_space: nvgpu_posix_io_delete_reg_space(g, gr_gpcs_swdx_dss_zbc_color_r_r(0)); -clean_up_fs_space: - nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_fs_reg_space); -clean_up_pes_tpc_mask: - nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_pes_tpc_mask_reg_space); -clean_up_priv_ring: - nvgpu_posix_io_unregister_reg_space(g, &gv11b_priv_ring_reg_space); -clean_up_gr: - nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_reg_space); -clean_up_fuse: - nvgpu_posix_io_unregister_reg_space(g, &gv11b_fuse_reg_space); -clean_up_top: - nvgpu_posix_io_unregister_reg_space(g, &gv11b_top_reg_space); -clean_up_master: - nvgpu_posix_io_unregister_reg_space(g, &gv11b_master_reg_space); +clean_up_reg_space: return -ENOMEM; } @@ -233,11 +233,5 @@ void test_gr_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g) nvgpu_posix_io_delete_reg_space(g, gr_gpcs_tpcs_pe_vaf_r()); nvgpu_posix_io_delete_reg_space(g, gr_pri_gpcs_gcc_dbg_r()); nvgpu_posix_io_delete_reg_space(g, gr_gpcs_swdx_dss_zbc_color_r_r(0)); - nvgpu_posix_io_unregister_reg_space(g, &gv11b_top_reg_space); - nvgpu_posix_io_unregister_reg_space(g, &gv11b_master_reg_space); - nvgpu_posix_io_unregister_reg_space(g, &gv11b_fuse_reg_space); - nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_reg_space); - nvgpu_posix_io_unregister_reg_space(g, &gv11b_priv_ring_reg_space); - nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_pes_tpc_mask_reg_space); - nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_fs_reg_space); + gr_io_delete_initialized_reg_space(m, g); }