gpu: nvgpu: update for gr_priv header cleanup

To avoid gr_priv inclusion outside gr unit for deferencing the
gr struct for gr->config pointer, add new call
nvgpu_gr_get_config_ptr which returns gr->config pointer.

Jira NVGPU-3218

Change-Id: Ibe6827f75c7621b72490f100c3a77baf02db2dd0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111737
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/ecc.c

@@ -22,11 +22,10 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/gr/config.h>
+#include <nvgpu/gr/gr.h>
 #include <nvgpu/ltc.h>
 #include <nvgpu/nvgpu_err.h>
 
-#include "common/gr/gr_priv.h"
-
 static void nvgpu_ecc_stat_add(struct gk20a *g, struct nvgpu_ecc_stat *stat)
 {
 	struct nvgpu_ecc *ecc = &g->ecc;
@@ -47,9 +46,9 @@ static void nvgpu_ecc_init(struct gk20a *g)
 int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
 		struct nvgpu_ecc_stat ***stat, const char *name)
 {
-	struct nvgpu_gr *gr = g->gr;
 	struct nvgpu_ecc_stat **stats;
-	u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr->config);
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
+	u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr_config);
 	u32 gpc, tpc;
 	int err = 0;
 
@@ -59,7 +58,7 @@ int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
 	}
 	for (gpc = 0; gpc < gpc_count; gpc++) {
 		stats[gpc] = nvgpu_kzalloc(g, sizeof(*stats[gpc]) *
-				nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc));
+				nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc));
 		if (stats[gpc] == NULL) {
 			err = -ENOMEM;
 			break;
@@ -77,7 +76,7 @@ int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
 
 	for (gpc = 0; gpc < gpc_count; gpc++) {
 		for (tpc = 0;
-		     tpc < nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc);
+		     tpc < nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc);
 		     tpc++) {
 			(void) snprintf(stats[gpc][tpc].name,
 					NVGPU_ECC_STAT_NAME_MAX_SIZE,
@@ -93,9 +92,9 @@ int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
 int nvgpu_ecc_counter_init_per_gpc(struct gk20a *g,
 		struct nvgpu_ecc_stat **stat, const char *name)
 {
-	struct nvgpu_gr *gr = g->gr;
 	struct nvgpu_ecc_stat *stats;
-	u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr->config);
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
+	u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr_config);
 	u32 gpc;
 
 	stats = nvgpu_kzalloc(g, sizeof(*stats) * gpc_count);
@@ -198,8 +197,8 @@ int nvgpu_ecc_counter_init_per_fbpa(struct gk20a *g,
 void nvgpu_ecc_free(struct gk20a *g)
 {
 	struct nvgpu_ecc *ecc = &g->ecc;
-	struct nvgpu_gr *gr = g->gr;
-	u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr->config);
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
+	u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr_config);
 	u32 i;
 
 	for (i = 0; i < gpc_count; i++) {

drivers/gpu/nvgpu/common/gr/gr.c

@@ -774,3 +774,8 @@ void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val)
 {
 	g->gr->fecs_feature_override_ecc_val = ecc_val;
 }
+
+struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g)
+{
+	return g->gr->config;
+}

drivers/gpu/nvgpu/common/gr/hwpm_map.c

@@ -32,7 +32,6 @@
 
 /* needed for pri_is_ppc_addr_shared */
 #include "hal/gr/gr/gr_pri_gk20a.h"
-#include "gr_priv.h"
 
 #define NV_PCFG_BASE		0x00088000U
 #define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200U

drivers/gpu/nvgpu/include/nvgpu/gr/gr.h

@@ -26,6 +26,7 @@
 #include <nvgpu/types.h>
 
 struct gk20a;
+struct nvgpu_gr_config;
 
 u32 nvgpu_gr_get_no_of_sm(struct gk20a *g);
 int nvgpu_gr_prepare_sw(struct gk20a *g);
@@ -46,4 +47,5 @@ int nvgpu_gr_halt_pipe(struct gk20a *g);
 void nvgpu_gr_remove_support(struct gk20a *g);
 void nvgpu_gr_sw_ready(struct gk20a *g, bool enable);
 void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val);
+struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g);
 #endif /* NVGPU_GR_H */

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -37,6 +37,7 @@
 #include <nvgpu/gr/config.h>
 #include <nvgpu/gr/zbc.h>
 #include <nvgpu/gr/zcull.h>
+#include <nvgpu/gr/gr.h>
 #include <nvgpu/gr/warpstate.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/pmu/pmgr.h>
@@ -291,6 +292,7 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 {
 	struct nvgpu_gpu_characteristics gpu;
 	long err = 0;
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
 
 	if (gk20a_busy(g)) {
 		nvgpu_err(g, "failed to power on gpu");
@@ -302,11 +304,11 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 	gpu.L2_cache_size = g->ops.ltc.determine_L2_size_bytes(g);
 	gpu.on_board_video_memory_size = 0; /* integrated GPU */
 
-	gpu.num_gpc = nvgpu_gr_config_get_gpc_count(g->gr->config);
-	gpu.max_gpc_count = nvgpu_gr_config_get_max_gpc_count(g->gr->config);
-	gpu.gpc_mask = nvgpu_gr_config_get_gpc_mask(g->gr->config);
+	gpu.num_gpc = nvgpu_gr_config_get_gpc_count(gr_config);
+	gpu.max_gpc_count = nvgpu_gr_config_get_max_gpc_count(gr_config);
+	gpu.gpc_mask = nvgpu_gr_config_get_gpc_mask(gr_config);
 
-	gpu.num_tpc_per_gpc = nvgpu_gr_config_get_max_tpc_per_gpc_count(g->gr->config);
+	gpu.num_tpc_per_gpc = nvgpu_gr_config_get_max_tpc_per_gpc_count(gr_config);
 
 	gpu.bus_type = NVGPU_GPU_BUS_TYPE_AXI; /* always AXI for now */
 
@@ -568,10 +570,10 @@ clean_up:
 static int gk20a_ctrl_get_tpc_masks(struct gk20a *g,
 				    struct nvgpu_gpu_get_tpc_masks_args *args)
 {
-	struct nvgpu_gr *gr = g->gr;
 	int err = 0;
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
 	const u32 gpc_tpc_mask_size = sizeof(u32) *
-		nvgpu_gr_config_get_max_gpc_count(gr->config);
+		nvgpu_gr_config_get_max_gpc_count(gr_config);
 
 	if (args->mask_buf_size > 0) {
 		size_t write_size = gpc_tpc_mask_size;
@@ -582,7 +584,7 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g,
 
 		err = copy_to_user((void __user *)(uintptr_t)
 			args->mask_buf_addr,
-			nvgpu_gr_config_get_gpc_tpc_mask_base(gr->config),
+			nvgpu_gr_config_get_gpc_tpc_mask_base(gr_config),
 			write_size);
 	}
 
@@ -821,11 +823,11 @@ static int gk20a_ctrl_vsm_mapping(struct gk20a *g,
 				    struct nvgpu_gpu_vsms_mapping *args)
 {
 	int err = 0;
-	struct nvgpu_gr *gr = g->gr;
 	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 	size_t write_size = no_of_sm *
 		sizeof(struct nvgpu_gpu_vsms_mapping_entry);
 	struct nvgpu_gpu_vsms_mapping_entry *vsms_buf;
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
 	u32 i;
 
 	vsms_buf = nvgpu_kzalloc(g, write_size);
@@ -834,7 +836,7 @@ static int gk20a_ctrl_vsm_mapping(struct gk20a *g,
 
 	for (i = 0; i < no_of_sm; i++) {
 		struct nvgpu_sm_info *sm_info =
-			nvgpu_gr_config_get_sm_info(gr->config, i);
+			nvgpu_gr_config_get_sm_info(gr_config, i);
 
 		vsms_buf[i].gpc_index =
 			nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
@@ -843,7 +845,7 @@ static int gk20a_ctrl_vsm_mapping(struct gk20a *g,
 				g->ops.gr.init.get_nonpes_aware_tpc(g,
 				nvgpu_gr_config_get_sm_info_gpc_index(sm_info),
 				nvgpu_gr_config_get_sm_info_tpc_index(sm_info),
-					gr->config);
+					gr_config);
 		else
 			vsms_buf[i].tpc_index =
 				nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
@@ -1664,6 +1666,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
 	struct nvgpu_gr_zcull_info *zcull_info;
 	struct nvgpu_gr_zbc_entry *zbc_val;
 	struct nvgpu_gr_zbc_query_params *zbc_tbl;
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
 	int err = 0;
 	u32 i;
 
@@ -1707,7 +1710,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
 		if (zcull_info == NULL)
 			return -ENOMEM;
 
-		err = g->ops.gr.zcull.get_zcull_info(g, g->gr->config,
+		err = g->ops.gr.zcull.get_zcull_info(g, gr_config,
 					g->gr->zcull, zcull_info);
 		if (err) {
 			nvgpu_kfree(g, zcull_info);

drivers/gpu/nvgpu/os/linux/ioctl_tsg.c

@@ -27,12 +27,11 @@
 #include <nvgpu/os_sched.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/gr/config.h>
+#include <nvgpu/gr/gr.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/tsg.h>
 #include <nvgpu/fifo.h>
 
-#include "common/gr/gr_priv.h"
-
 #include "platform_gk20a.h"
 #include "ioctl_tsg.h"
 #include "ioctl_channel.h"
@@ -64,7 +63,7 @@ static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
 	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
 	struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
 	struct nvgpu_channel *ch;
-	struct nvgpu_gr *gr = g->gr;
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
 	int err = 0;
 
 	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
@@ -88,7 +87,7 @@ static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
 
 	if (arg->tpc_pg_enabled && (!tsg->tpc_num_initialized)) {
 		if ((arg->num_active_tpcs >
-				nvgpu_gr_config_get_max_tpc_count(gr->config)) ||
+				nvgpu_gr_config_get_max_tpc_count(gr_config)) ||
 		    !(arg->num_active_tpcs)) {
 			nvgpu_err(g, "Invalid num of active TPCs");
 			err = -EINVAL;

drivers/gpu/nvgpu/os/linux/sysfs.c

@@ -874,18 +874,18 @@ static ssize_t tpc_fs_mask_store(struct device *dev,
 	struct device_attribute *attr, const char *buf, size_t count)
 {
 	struct gk20a *g = get_gk20a(dev);
-	struct nvgpu_gr_config *config = g->gr->config;
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
 	unsigned long val = 0;
 
 	if (kstrtoul(buf, 10, &val) < 0)
 		return -EINVAL;
 
-	if (nvgpu_gr_config_get_gpc_tpc_mask_base(config) != NULL)
+	if (nvgpu_gr_config_get_gpc_tpc_mask_base(gr_config) != NULL)
 		return -ENODEV;
 
-	if (val && val != nvgpu_gr_config_get_gpc_tpc_mask(config, 0) &&
+	if (val && val != nvgpu_gr_config_get_gpc_tpc_mask(gr_config, 0) &&
 		g->ops.gr.set_gpc_tpc_mask) {
-		nvgpu_gr_config_set_gpc_tpc_mask(config, 0, val);
+		nvgpu_gr_config_set_gpc_tpc_mask(gr_config, 0, val);
 		g->tpc_fs_mask_user = val;
 
 		g->ops.gr.set_gpc_tpc_mask(g, 0);
@@ -897,7 +897,7 @@ static ssize_t tpc_fs_mask_store(struct device *dev,
 		nvgpu_gr_falcon_remove_support(g, g->gr->falcon);
 		g->gr->falcon = NULL;
 
-		nvgpu_gr_config_deinit(g, g->gr->config);
+		nvgpu_gr_config_deinit(g, gr_config);
 		/* Cause next poweron to reinit just gr */
 		nvgpu_gr_sw_ready(g, false);
 	}
@@ -909,7 +909,7 @@ static ssize_t tpc_fs_mask_read(struct device *dev,
 	struct device_attribute *attr, char *buf)
 {
 	struct gk20a *g = get_gk20a(dev);
-	struct nvgpu_gr *gr = g->gr;
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
 	u32 gpc_index;
 	u32 tpc_fs_mask = 0;
 	int err = 0;
@@ -919,12 +919,12 @@ static ssize_t tpc_fs_mask_read(struct device *dev,
 		return err;
 
 	for (gpc_index = 0;
-	     gpc_index < nvgpu_gr_config_get_gpc_count(gr->config);
+	     gpc_index < nvgpu_gr_config_get_gpc_count(gr_config);
 	     gpc_index++) {
 		if (g->ops.gr.config.get_gpc_tpc_mask)
 			tpc_fs_mask |=
-				g->ops.gr.config.get_gpc_tpc_mask(g, gr->config, gpc_index) <<
-				(nvgpu_gr_config_get_max_tpc_per_gpc_count(gr->config) * gpc_index);
+				g->ops.gr.config.get_gpc_tpc_mask(g, gr_config, gpc_index) <<
+				(nvgpu_gr_config_get_max_tpc_per_gpc_count(gr_config) * gpc_index);
 	}
 
 	gk20a_idle(g);