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gpu: nvgpu: Move gk20a_gr_nonstall_isr function to hal

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Change gk20a_gr_nonstall_isr function to hal under hal.gr.intr

Use nvgpu_gr_gpc_offset and nvgpu_gr_tpc_offset call in
gm20b_gr_intr_handle_tex_exception function.

Update gk20a_gr_nonstall_isr call as g->ops.gr.intr.nonstall_isr

JIRA NVGPU-3016

Change-Id: I9ff39cf1a99bf5b3d215cda6bc68fab1ecae51e3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088133
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-04-02 13:26:57 -07:00
committed by mobile promotions
parent 9abe4608b4
commit 4b433b528e
10 changed files with 26 additions and 23 deletions
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17
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -2293,23 +2293,6 @@ int gk20a_gr_isr(struct gk20a *g)
return 0;
}
u32 gk20a_gr_nonstall_isr(struct gk20a *g)
{
u32 ops = 0;
u32 gr_intr = gk20a_readl(g, gr_intr_nonstall_r());
nvgpu_log(g, gpu_dbg_intr, "pgraph nonstall intr %08x", gr_intr);
if ((gr_intr & gr_intr_nonstall_trap_pending_f()) != 0U) {
/* Clear the interrupt */
gk20a_writel(g, gr_intr_nonstall_r(),
gr_intr_nonstall_trap_pending_f());
ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE |
GK20A_NONSTALL_OPS_POST_EVENTS);
}
return ops;
}
int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size)
{
BUG_ON(size == NULL);