nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: add BVEC test for LTC isr

Browse Source 
Add BVEC tests for following common.ltc unit API:
gops_ltc_intr.isr

Add unit test for boundary value check for ltc parameter of
the LTC isr.

JIRA NVGPU-6398

Change-Id: I0e075a3244d969d11faa4fd99e7e364218da6e30
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2549802
(cherry picked from commit 3133a7173b0853a699e4ebf2fc50e866e3ac6211)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623636
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2021-06-24 22:46:22 +05:30
committed by mobile promotions
parent 04587333ca
commit 4b73eb8a43
12 changed files with 155 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
View File

@@ -30,7 +30,7 @@
struct gk20a;
void ga10b_ltc_intr_configure(struct gk20a *g);
void ga10b_ltc_intr_isr(struct gk20a *g, u32 ltc);
int ga10b_ltc_intr_isr(struct gk20a *g, u32 ltc);
void ga10b_ltc_intr3_configure_extra(struct gk20a *g, u32 *reg);
void ga10b_ltc_intr3_interrupts(struct gk20a *g, u32 ltc, u32 slice,
u32 ltc_intr3);

8
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
View File

@@ -1078,13 +1078,19 @@ void ga10b_ltc_intr_handle_lts_intr(struct gk20a *g, u32 ltc, u32 slice)
reg_value);
}
void ga10b_ltc_intr_isr(struct gk20a *g, u32 ltc)
int ga10b_ltc_intr_isr(struct gk20a *g, u32 ltc)
{
u32 slice;
if (ltc >= nvgpu_ltc_get_ltc_count(g)) {
return -ENODEV;
}
for (slice = 0U; slice < g->ltc->slices_per_ltc; slice++) {
ga10b_ltc_intr_handle_lts_intr(g, ltc, slice);
ga10b_ltc_intr_handle_lts_intr2(g, ltc, slice);
ga10b_ltc_intr_handle_lts_intr3(g, ltc, slice);
}
return 0;
}

10
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gm20b.c
View File

@@ -1,7 +1,7 @@
/*
* GM20B L2 INTR
*
* Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022 NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -61,12 +61,18 @@ static void gm20b_ltc_intr_handle_lts_interrupts(struct gk20a *g,
nvgpu_safe_mult_u32(lts_stride, slice))), ltc_intr);
}
void gm20b_ltc_intr_isr(struct gk20a *g, u32 ltc)
int gm20b_ltc_intr_isr(struct gk20a *g, u32 ltc)
{
u32 slice;
if (ltc >= nvgpu_ltc_get_ltc_count(g)) {
return -ENODEV;
}
for (slice = 0U; slice < g->ltc->slices_per_ltc; slice =
nvgpu_safe_add_u32(slice, 1U)) {
gm20b_ltc_intr_handle_lts_interrupts(g, ltc, slice);
}
return 0;
}

4
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gm20b.h
View File

@@ -1,7 +1,7 @@
/*
* GM20B L2 INTR
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -30,6 +30,6 @@
struct gk20a;
void gm20b_ltc_intr_configure(struct gk20a *g);
void gm20b_ltc_intr_isr(struct gk20a *g, u32 ltc);
int gm20b_ltc_intr_isr(struct gk20a *g, u32 ltc);
#endif

10
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c
View File

@@ -1,7 +1,7 @@
/*
* GP10B L2 INTR
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -33,14 +33,20 @@
#include "ltc_intr_gp10b.h"
#include "ltc_intr_gm20b.h"
void gp10b_ltc_intr_isr(struct gk20a *g, u32 ltc)
int gp10b_ltc_intr_isr(struct gk20a *g, u32 ltc)
{
u32 slice;
if (ltc >= nvgpu_ltc_get_ltc_count(g)) {
return -ENODEV;
}
for (slice = 0U; slice < g->ltc->slices_per_ltc; slice =
nvgpu_safe_add_u32(slice, 1U)) {
gp10b_ltc_intr_handle_lts_interrupts(g, ltc, slice);
}
return 0;
}
void gp10b_ltc_intr_configure(struct gk20a *g)

4
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.h
View File

@@ -1,7 +1,7 @@
/*
* GP10B L2 INTR
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -32,7 +32,7 @@ struct gk20a;
void gp10b_ltc_intr_handle_lts_interrupts(struct gk20a *g, u32 ltc, u32 slice);
#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
void gp10b_ltc_intr_configure(struct gk20a *g);
void gp10b_ltc_intr_isr(struct gk20a *g, u32 ltc);
int gp10b_ltc_intr_isr(struct gk20a *g, u32 ltc);
#endif
#endif

4
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.h
View File

@@ -1,7 +1,7 @@
/*
* GV11B L2 INTR
*
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -30,7 +30,7 @@
struct gk20a;
void gv11b_ltc_intr_configure(struct gk20a *g);
void gv11b_ltc_intr_isr(struct gk20a *g, u32 ltc);
int gv11b_ltc_intr_isr(struct gk20a *g, u32 ltc);
#ifdef CONFIG_NVGPU_NON_FUSA
void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable);
#endif

8
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c
View File

@@ -341,11 +341,17 @@ static void gv11b_ltc_intr_handle_lts_interrupts(struct gk20a *g,
gv11b_ltc_intr_handle_ecc_sec_ded_interrupts(g, ltc, slice);
}
void gv11b_ltc_intr_isr(struct gk20a *g, u32 ltc)
int gv11b_ltc_intr_isr(struct gk20a *g, u32 ltc)
{
u32 slice;
if (ltc >= nvgpu_ltc_get_ltc_count(g)) {
return -ENODEV;
}
for (slice = 0U; slice < g->ltc->slices_per_ltc; slice++) {
gv11b_ltc_intr_handle_lts_interrupts(g, ltc, slice);
}
return 0;
}

2
drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
View File

@@ -196,7 +196,7 @@ struct gops_ltc_intr {
* @return 0 in case of success, < 0 in case of failure.
* @retval -ENODEV if invalid LTC number specified.
*/
void (*isr)(struct gk20a *g, u32 ltc);
int (*isr)(struct gk20a *g, u32 ltc);
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
void (*configure)(struct gk20a *g);