diff --git a/drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c b/drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c
index b80aa0d47..f1e3818f6 100644
--- a/drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c
+++ b/drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c
@@ -23,6 +23,7 @@
 #include <nvgpu/log.h>
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/nvgpu_err.h>
 
 #include "ptimer_gk20a.h"
 
@@ -31,6 +32,9 @@
 void gk20a_ptimer_isr(struct gk20a *g)
 {
 	u32 save0, save1, fecs_errcode = 0;
+	int ret = 0;
+	u32 inst = 0U;
+	u32 error_addr;
 
 	save0 = gk20a_readl(g, timer_pri_timeout_save_0_r());
 	if (timer_pri_timeout_save_0_fecs_tgt_v(save0) != 0U) {
@@ -43,9 +47,10 @@ void gk20a_ptimer_isr(struct gk20a *g)
 	}
 
 	save1 = gk20a_readl(g, timer_pri_timeout_save_1_r());
+	error_addr = timer_pri_timeout_save_0_addr_v(save0) << 2;
 	nvgpu_err(g, "PRI timeout: ADR 0x%08x "
 		"%s  DATA 0x%08x",
-		timer_pri_timeout_save_0_addr_v(save0) << 2,
+		error_addr,
 		(timer_pri_timeout_save_0_write_v(save0) != 0U) ?
 		"WRITE" : "READ", save1);
 
@@ -58,6 +63,24 @@ void gk20a_ptimer_isr(struct gk20a *g)
 			g->ops.priv_ring.decode_error_code(g,
 						fecs_errcode);
 		}
+		/* FECS was the target of PRI access */
+		inst = 1U;
+		/* SAVE_0_ADDR cannot be used in this case */
+		error_addr = 0U;
+	}
+
+	if (g->ops.ptimer.err_ops.report_timeout_err != NULL) {
+		ret = g->ops.ptimer.err_ops.report_timeout_err(g,
+				NVGPU_ERR_MODULE_PRI,
+				inst,
+				GPU_PRI_TIMEOUT_ERROR,
+				error_addr,
+				fecs_errcode);
+		if (ret != 0) {
+			nvgpu_err(g, "Failed to report PRI Timout error: "
+					"inst=%u, err_addr=%u, err_code=%u",
+					inst, error_addr, fecs_errcode);
+		}
 	}
 }
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index e9d63f376..36e95ad0c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1448,6 +1448,11 @@ struct gpu_ops {
 		int (*get_timestamps_zipper)(struct gk20a *g,
 			u32 source_id, u32 count,
 			struct nvgpu_cpu_time_correlation_sample *samples);
+		struct {
+			int (*report_timeout_err)(struct gk20a *g,
+					u32 hw_id, u32 inst, u32 err_id,
+					u32 err_addr, u32 error_code);
+		} err_ops;
 	} ptimer;
 
 	struct {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
index 728202482..a37716f6a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
@@ -33,8 +33,8 @@
 #define NVGPU_ERR_MODULE_PGRAPH		7U
 #define NVGPU_ERR_MODULE_LTC		8U
 #define NVGPU_ERR_MODULE_HUBMMU		9U
+#define NVGPU_ERR_MODULE_PRI		10U
 #define NVGPU_ERR_MODULE_CE		11U
-#define NVGPU_ERR_MODULE_INVALID	12U
 
 #define GPU_HOST_PFIFO_BIND_ERROR		0U
 #define GPU_HOST_PFIFO_SCHED_ERROR		1U
@@ -75,20 +75,17 @@
 #define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED	17U
 #define GPU_SM_ICACHE_L1_PREDECODE_ECC_CORRECTED	18U
 #define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED	19U
-#define GPU_SM_INVALID_ERROR				20U
 
 #define GPU_FECS_FALCON_IMEM_ECC_CORRECTED	0U
 #define GPU_FECS_FALCON_IMEM_ECC_UNCORRECTED	1U
 #define GPU_FECS_FALCON_DMEM_ECC_CORRECTED	2U
 #define GPU_FECS_FALCON_DMEM_ECC_UNCORRECTED	3U
 #define GPU_FECS_HOST_INT_EXCEPTION		4U
-#define GPU_FECS_INVALID_ERROR			5U
 
 #define GPU_GPCCS_FALCON_IMEM_ECC_CORRECTED	0U
 #define GPU_GPCCS_FALCON_IMEM_ECC_UNCORRECTED	1U
 #define GPU_GPCCS_FALCON_DMEM_ECC_CORRECTED	2U
 #define GPU_GPCCS_FALCON_DMEM_ECC_UNCORRECTED	3U
-#define GPU_GPCCS_INVALID_ERROR			4U
 
 #define GPU_MMU_L1TLB_ECC_CORRECTED		0U
 #define GPU_MMU_L1TLB_ECC_UNCORRECTED		1U
@@ -96,17 +93,14 @@
 #define GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED	3U
 #define GPU_MMU_L1TLB_FA_DATA_ECC_CORRECTED	4U
 #define GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED	5U
-#define GPU_MMU_INVALID_ERROR			6U
 
 #define GPU_GCC_L15_ECC_CORRECTED		0U
 #define GPU_GCC_L15_ECC_UNCORRECTED		1U
-#define GPU_GCC_INVALID_ERROR			2U
 
 #define GPU_PMU_FALCON_IMEM_ECC_CORRECTED	0U
 #define GPU_PMU_FALCON_IMEM_ECC_UNCORRECTED	1U
 #define GPU_PMU_FALCON_DMEM_ECC_CORRECTED	2U
 #define GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED	3U
-#define GPU_PMU_INVALID_ERROR			4U
 
 #define GPU_PGRAPH_FE_EXCEPTION			0U
 #define GPU_PGRAPH_MEMFMT_EXCEPTION		1U
@@ -119,7 +113,6 @@
 #define GPU_PGRAPH_GPC_EXCEPTION		8U
 #define GPU_PGRAPH_BE_EXCEPTION			9U
 #define GPU_PGRAPH_MPC_EXCEPTION		10U
-#define GPU_PGRAPH_INVALID_ERROR		11U
 
 #define GPU_LTC_CACHE_DSTG_ECC_CORRECTED	0U
 #define GPU_LTC_CACHE_DSTG_ECC_UNCORRECTED	1U
@@ -129,7 +122,6 @@
 #define GPU_LTC_CACHE_RSTG_ECC_UNCORRECTED	5U
 #define GPU_LTC_CACHE_DSTG_BE_ECC_CORRECTED	6U
 #define GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED	7U
-#define GPU_LTC_INVALID_ERROR			8U
 
 #define GPU_HUBMMU_L2TLB_SA_DATA_ECC_CORRECTED		0U
 #define GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED	1U
@@ -139,7 +131,8 @@
 #define GPU_HUBMMU_PTE_DATA_ECC_UNCORRECTED		5U
 #define GPU_HUBMMU_PDE0_DATA_ECC_CORRECTED		6U
 #define GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED		7U
-#define GPU_HUBMMU_INVALID_ERROR			8U
+
+#define GPU_PRI_TIMEOUT_ERROR	0U
 
 #define GPU_CE_LAUNCH_ERROR			0U
 #define GPU_CE_BLOCK_PIPE			1U