diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
index dd01b3376..32b103062 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
@@ -75,4 +75,6 @@ u32 ga10b_pbdma_intr_1_en_set_tree_mask(void);
 u32 ga10b_pbdma_intr_1_en_clear_tree_mask(void);
 void ga10b_pbdma_report_error(struct gk20a *g, u32 pbdma_id,
 		u32 pbdma_intr_0);
+void ga10b_pbdma_dump_intr_0(struct gk20a *g, u32 pbdma_id,
+				u32 pbdma_intr_0);
 #endif /* NVGPU_PBDMA_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
index a1264273b..c82e00fae 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
@@ -230,7 +230,7 @@ void ga10b_pbdma_disable_and_clear_all_intr(struct gk20a *g)
 	}
 }
 
-static void ga10b_pbdma_dump_intr_0(struct gk20a *g, u32 pbdma_id,
+void ga10b_pbdma_dump_intr_0(struct gk20a *g, u32 pbdma_id,
 				u32 pbdma_intr_0)
 {
 	u32 header = nvgpu_readl(g, pbdma_pb_header_r(pbdma_id));
@@ -430,7 +430,9 @@ static bool ga10b_pbdma_handle_intr_0_legacy(struct gk20a *g, u32 pbdma_id,
 				pbdma_intr_fault_type_desc[bit]);
 		}
 
-		ga10b_pbdma_dump_intr_0(g, pbdma_id, pbdma_intr_0);
+		if (g->ops.pbdma.dump_intr_0 != NULL) {
+			g->ops.pbdma.dump_intr_0(g, pbdma_id, pbdma_intr_0);
+		}
 
 		recover = true;
 	}
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index f4aba93bd..ecab8cb04 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -1056,6 +1056,7 @@ static const struct gops_pbdma ga100_ops_pbdma = {
 	.handle_intr_0 = ga10b_pbdma_handle_intr_0,
 	.handle_intr_1 = ga10b_pbdma_handle_intr_1,
 	.handle_intr = ga10b_pbdma_handle_intr,
+	.dump_intr_0 = ga10b_pbdma_dump_intr_0,
 	.set_clear_intr_offsets = ga100_pbdma_set_clear_intr_offsets,
 	.read_data = ga100_pbdma_read_data,
 	.reset_header = ga10b_pbdma_reset_header,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index f91e45240..85ba066cb 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -1074,6 +1074,7 @@ static const struct gops_pbdma ga10b_ops_pbdma = {
 	.handle_intr_0 = ga10b_pbdma_handle_intr_0,
 	.handle_intr_1 = ga10b_pbdma_handle_intr_1,
 	.handle_intr = ga10b_pbdma_handle_intr,
+	.dump_intr_0 = ga10b_pbdma_dump_intr_0,
 	.set_clear_intr_offsets = ga10b_pbdma_set_clear_intr_offsets,
 	.read_data = ga10b_pbdma_read_data,
 	.reset_header = ga10b_pbdma_reset_header,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
index eaf49320f..0d40ca2b3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
@@ -56,6 +56,8 @@ struct gops_pbdma {
 			u32 pbdma_id, u32 pbdma_intr_1,
 			u32 *error_notifier);
 	int (*handle_intr)(struct gk20a *g, u32 pbdma_id, bool recover);
+	void (*dump_intr_0)(struct gk20a *g, u32 pbdma_id,
+				u32 pbdma_intr_0);
 	u32 (*set_clear_intr_offsets) (struct gk20a *g,
 			u32 set_clear_size);
 	u32 (*get_signature)(struct gk20a *g);