From 4bbc7664544e5efb15970f9a32e403af0b1afa91 Mon Sep 17 00:00:00 2001 From: Rajesh Devaraj Date: Tue, 14 Feb 2023 08:40:56 +0000 Subject: [PATCH] gpu: nvgpu: add intr_0_pbcrc_pending gops for pbdma Add intr_0_pbcrc_pending hal to avoid duplication of the entire function for new chips. JIRA NVGPU-9325 Change-Id: Ia08ce7761ac5b9a1af1166efbc1ecba97b54fc87 Signed-off-by: Rajesh Devaraj Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857919 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h | 1 + drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c | 15 +++++++++++---- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 1 + drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h | 1 + 5 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h index 0d88b1c12..28ecf46cf 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h @@ -81,4 +81,5 @@ void ga10b_pbdma_dump_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0); bool ga10b_pbdma_is_sw_method_subch(struct gk20a *g, u32 pbdma_id, u32 pbdma_method_index); +u32 ga10b_pbdma_intr_0_pbcrc_pending(void); #endif /* NVGPU_PBDMA_GA10B_H */ diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c index ed4827ae0..07a111d25 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c @@ -453,10 +453,12 @@ static bool ga10b_pbdma_handle_intr_0_legacy(struct gk20a *g, u32 pbdma_id, recover = true; } - if ((pbdma_intr_0 & pbdma_intr_0_pbcrc_pending_f()) != 0U) { - *error_notifier = - NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH; - recover = true; + if (g->ops.pbdma.intr_0_pbcrc_pending != NULL) { + if ((pbdma_intr_0 & g->ops.pbdma.intr_0_pbcrc_pending()) != 0U) { + *error_notifier = + NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH; + recover = true; + } } if ((pbdma_intr_0 & pbdma_intr_0_device_pending_f()) != 0U) { @@ -624,6 +626,11 @@ u32 ga10b_pbdma_get_num_of_pbdmas(void) return pbdma_cfg0__size_1_v(); } +u32 ga10b_pbdma_intr_0_pbcrc_pending(void) +{ + return pbdma_intr_0_pbcrc_pending_f(); +} + bool ga10b_pbdma_handle_intr_0_acquire(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0, u32 *error_notifier) { diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index f4ebf51e1..5a7fc62ed 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -1055,6 +1055,7 @@ static const struct gops_pbdma ga100_ops_pbdma = { #endif .handle_intr_0 = ga10b_pbdma_handle_intr_0, .handle_intr_0_acquire = ga10b_pbdma_handle_intr_0_acquire, + .intr_0_pbcrc_pending = ga10b_pbdma_intr_0_pbcrc_pending, .handle_intr_1 = ga10b_pbdma_handle_intr_1, .handle_intr = ga10b_pbdma_handle_intr, .dump_intr_0 = ga10b_pbdma_dump_intr_0, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 660eb3e6b..bf82b6fc6 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1073,6 +1073,7 @@ static const struct gops_pbdma ga10b_ops_pbdma = { #endif .handle_intr_0 = ga10b_pbdma_handle_intr_0, .handle_intr_0_acquire = ga10b_pbdma_handle_intr_0_acquire, + .intr_0_pbcrc_pending = ga10b_pbdma_intr_0_pbcrc_pending, .handle_intr_1 = ga10b_pbdma_handle_intr_1, .handle_intr = ga10b_pbdma_handle_intr, .dump_intr_0 = ga10b_pbdma_dump_intr_0, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h index dab9281e1..ccf0c17e9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h @@ -100,6 +100,7 @@ struct gops_pbdma { u32 pbdma_intr_0, u32 *error_notifier); bool (*is_sw_method_subch)(struct gk20a *g, u32 pbdma_id, u32 pbdma_method_index); + u32 (*intr_0_pbcrc_pending)(void); /** NON FUSA */ void (*syncpt_debug_dump)(struct gk20a *g,