gpu: nvgpu: Add hals for router_perfmon_regs_base

gv11b onwards add hals
        get_hwpm_gpcrouter_perfmon_regs_base
        get_hwpm_fbprouter_perfmon_regs_base

And remove the ga10b version of same as that is redundant.

This is preparatory patch to update the gr_gv11b_pri_pmmgpcrouter_addr
and gr_gv11b_pri_pmmfbprouter_addr with the hals

JIRA NVGPU-9073

Change-Id: I8b04f9b61784ca2c09b248655435ea7a7ab92926
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2828584
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>

drivers/gpu/nvgpu/hal/init/hal_ga100.c

@@ -1505,8 +1505,8 @@ static const struct gops_perf ga100_ops_perf = {
 	.update_get_put = ga10b_perf_update_get_put,
 	.get_hwpm_fbp_perfmon_regs_base = ga10b_get_hwpm_fbp_perfmon_regs_base,
 	.get_hwpm_gpc_perfmon_regs_base = ga10b_get_hwpm_gpc_perfmon_regs_base,
-	.get_hwpm_fbprouter_perfmon_regs_base = ga10b_get_hwpm_fbprouter_perfmon_regs_base,
+	.get_hwpm_fbprouter_perfmon_regs_base = gv11b_get_hwpm_fbprouter_perfmon_regs_base,
-	.get_hwpm_gpcrouter_perfmon_regs_base = ga10b_get_hwpm_gpcrouter_perfmon_regs_base,
+	.get_hwpm_gpcrouter_perfmon_regs_base = gv11b_get_hwpm_gpcrouter_perfmon_regs_base,
 	.get_hwpm_sys_perfmon_regs = ga100_perf_get_hwpm_sys_perfmon_regs,
 	.get_hwpm_gpc_perfmon_regs = ga100_perf_get_hwpm_gpc_perfmon_regs,
 	.get_hwpm_fbp_perfmon_regs = ga100_perf_get_hwpm_fbp_perfmon_regs,

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -1535,7 +1535,8 @@ static const struct gops_perf ga10b_ops_perf = {
 	.get_hwpm_sys_perfmon_regs = ga10b_perf_get_hwpm_sys_perfmon_regs,
 	.get_hwpm_gpc_perfmon_regs = ga10b_perf_get_hwpm_gpc_perfmon_regs,
 	.get_hwpm_fbp_perfmon_regs = ga10b_perf_get_hwpm_fbp_perfmon_regs,
-	.get_hwpm_gpcrouter_perfmon_regs_base = ga10b_get_hwpm_gpcrouter_perfmon_regs_base,
+	.get_hwpm_gpcrouter_perfmon_regs_base = gv11b_get_hwpm_gpcrouter_perfmon_regs_base,
+	.get_hwpm_fbprouter_perfmon_regs_base = gv11b_get_hwpm_fbprouter_perfmon_regs_base,
 	.set_pmm_register = gv11b_perf_set_pmm_register,
 	.get_num_hwpm_perfmon = ga10b_perf_get_num_hwpm_perfmon,
 	.init_hwpm_pmm_register = ga10b_perf_init_hwpm_pmm_register,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -1321,6 +1321,8 @@ static const struct gops_perf gv11b_ops_perf = {
 	.get_hwpm_sys_perfmon_regs = gv11b_perf_get_hwpm_sys_perfmon_regs,
 	.get_hwpm_gpc_perfmon_regs = gv11b_perf_get_hwpm_gpc_perfmon_regs,
 	.get_hwpm_fbp_perfmon_regs = gv11b_perf_get_hwpm_fbp_perfmon_regs,
+	.get_hwpm_gpcrouter_perfmon_regs_base = gv11b_get_hwpm_gpcrouter_perfmon_regs_base,
+	.get_hwpm_fbprouter_perfmon_regs_base = gv11b_get_hwpm_fbprouter_perfmon_regs_base,
 	.set_pmm_register = gv11b_perf_set_pmm_register,
 	.get_num_hwpm_perfmon = gv11b_perf_get_num_hwpm_perfmon,
 	.init_hwpm_pmm_register = gv11b_perf_init_hwpm_pmm_register,

drivers/gpu/nvgpu/hal/perf/perf_ga10b.c

@@ -519,24 +519,13 @@ u32 ga10b_get_hwpm_fbp_perfmon_regs_base(struct gk20a *g)
 	(void)g;
 	return perf_pmmfbp_base_v();
 }
+
 u32 ga10b_get_hwpm_gpc_perfmon_regs_base(struct gk20a *g)
 {
 	(void)g;
 	return perf_pmmgpc_base_v();
 }
 
-u32 ga10b_get_hwpm_fbprouter_perfmon_regs_base(struct gk20a *g)
-{
-	(void)g;
-	return perf_pmmfbprouter_base_v();
-}
-
-u32 ga10b_get_hwpm_gpcrouter_perfmon_regs_base(struct gk20a *g)
-{
-	(void)g;
-	return perf_pmmgpcrouter_base_v();
-}
-
 void ga10b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
 				u32 *num_fbp_perfmon, u32 *num_gpc_perfmon)
 {

drivers/gpu/nvgpu/hal/perf/perf_ga10b.h

@@ -56,8 +56,6 @@ const u32 *ga10b_perf_get_hwpm_fbp_perfmon_regs(u32 *count);
 
 u32 ga10b_get_hwpm_fbp_perfmon_regs_base(struct gk20a *g);
 u32 ga10b_get_hwpm_gpc_perfmon_regs_base(struct gk20a *g);
-u32 ga10b_get_hwpm_fbprouter_perfmon_regs_base(struct gk20a *g);
-u32 ga10b_get_hwpm_gpcrouter_perfmon_regs_base(struct gk20a *g);
 
 void ga10b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
 		u32 *num_fbp_perfmon, u32 *num_gpc_perfmon);

drivers/gpu/nvgpu/hal/perf/perf_gv11b.c

@@ -185,6 +185,18 @@ u32 gv11b_perf_get_pmmfbprouter_per_chiplet_offset(void)
 	return (perf_pmmfbprouter_extent_v() - perf_pmmfbprouter_base_v() + 1U);
 }
 
+u32 gv11b_get_hwpm_fbprouter_perfmon_regs_base(struct gk20a *g)
+{
+	(void)g;
+	return perf_pmmfbprouter_base_v();
+}
+
+u32 gv11b_get_hwpm_gpcrouter_perfmon_regs_base(struct gk20a *g)
+{
+	(void)g;
+	return perf_pmmgpcrouter_base_v();
+}
+
 static const u32 hwpm_sys_perfmon_regs[] =
 {
 	/* This list is autogenerated. Do not edit. */

drivers/gpu/nvgpu/hal/perf/perf_gv11b.h

@@ -53,6 +53,8 @@ u32 gv11b_perf_get_pmmgpc_per_chiplet_offset(void);
 u32 gv11b_perf_get_pmmgpcrouter_per_chiplet_offset(void);
 u32 gv11b_perf_get_pmmfbp_per_chiplet_offset(void);
 u32 gv11b_perf_get_pmmfbprouter_per_chiplet_offset(void);
+u32 gv11b_get_hwpm_fbprouter_perfmon_regs_base(struct gk20a *g);
+u32 gv11b_get_hwpm_gpcrouter_perfmon_regs_base(struct gk20a *g);
 
 const u32 *gv11b_perf_get_hwpm_sys_perfmon_regs(u32 *count);
 const u32 *gv11b_perf_get_hwpm_gpc_perfmon_regs(u32 *count);