gpu: nvgpu: vgpu: add freq capping support

Currently callbacks from the PM_QOS framework (for
thermal events), result in a RPC call to set GPU frequency.

Since the governor will now be responsible for setting desired
rate, the max PM_QOS callback will now cap the possible
GPU frequency w/ a new RPC call to the server. The server
is responsible for setting the ultimate frequency
based on the cap & desired rates.

Jira VFND-3699

Change-Id: I806e309c40abc2f1381b6a23f2d898cfe26f9794
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1295543
(cherry picked from commit e81693c6e087f8f10a985be83715042fc590d6db)
Reviewed-on: http://git-master/r/1282467
(cherry picked from commit 7b4e0db647572e82a8d53e823c36b465781f4942)
Reviewed-on: http://git-master/r/1321836
(cherry picked from commit 57dafc08a5)
Reviewed-on: http://git-master/r/1313469
Tested-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/vgpu/clk_vgpu.c

@@ -128,3 +128,26 @@ int vgpu_clk_get_freqs(struct device *dev,
 
 	return 0;
 }
+
+int vgpu_clk_cap_rate(struct device *dev, unsigned long rate)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct gk20a *g = platform->g;
+	struct tegra_vgpu_cmd_msg msg = {};
+	struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate;
+	int err = 0;
+
+	gk20a_dbg_fn("");
+
+	msg.cmd = TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE;
+	msg.handle = vgpu_get_handle(g);
+	p->rate = (u32)rate;
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	err = err ? err : msg.ret;
+	if (err) {
+		nvgpu_err(g, "%s failed - %d", __func__, err);
+		return err;
+	}
+
+	return 0;
+}

drivers/gpu/nvgpu/vgpu/clk_vgpu.h

@@ -20,4 +20,5 @@ void vgpu_init_clk_support(struct gk20a *g);
 long vgpu_clk_round_rate(struct device *dev, unsigned long rate);
 int vgpu_clk_get_freqs(struct device *dev,
 			unsigned long **freqs, int *num_freqs);
+int vgpu_clk_cap_rate(struct device *dev, unsigned long rate);
 #endif

drivers/gpu/nvgpu/vgpu/vgpu.c

@@ -516,20 +516,13 @@ static int vgpu_qos_notify(struct notifier_block *nb,
 			container_of(nb, struct gk20a_scale_profile,
 			qos_notify_block);
 	struct gk20a *g = get_gk20a(profile->dev);
-	struct tegra_vgpu_cmd_msg msg = {};
-	struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate;
 	u32 max_freq;
 	int err;
 
 	gk20a_dbg_fn("");
 
 	max_freq = (u32)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS);
-
+	err = vgpu_clk_cap_rate(profile->dev, max_freq);
-	msg.cmd = TEGRA_VGPU_CMD_SET_GPU_CLK_RATE;
-	msg.handle = vgpu_get_handle_from_dev(profile->dev);
-	p->rate = max_freq;
-	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
-	err = err ? err : msg.ret;
 	if (err)
 		nvgpu_err(g, "%s failed, err=%d", __func__, err);
 

include/linux/tegra_vgpu.h

@@ -102,6 +102,7 @@ enum {
 	TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68,
 	TEGRA_VGPU_CMD_GET_GPU_CLK_RATE = 69,
 	TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE = 70,
+	TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE = 71,
 	TEGRA_VGPU_CMD_PROF_MGT = 72,
 	TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74,
 };