From 4e1769097526e5203f7c18a663ab3c29f5568ae5 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Wed, 6 Feb 2019 09:26:46 -0800 Subject: [PATCH] gpu: nvgpu: Discard coherency check on gmmu With MSS Nvlink set for force snoop, check for the coherency flag in gmmu attribute and setting pte aperture to coherent type based on that checking is not relevant. coherent variable removed from nvgpu_gmmu_attrs struct. bug 200473147 Change-Id: I9bab92ddebfb3a10dbddf1aa13d34bf806e568d7 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2013212 Reviewed-by: svc-misra-checker Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/mm/gmmu/page_table.c | 13 +------------ drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 3 +-- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 3 +-- drivers/gpu/nvgpu/include/nvgpu/gmmu.h | 4 +--- include/uapi/linux/nvgpu.h | 2 ++ 5 files changed, 6 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c index 42393b688..da35abb26 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c @@ -713,7 +713,7 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm, "vm=%s " "%-5s GPU virt %#-12llx +%#-9llx phys %#-12llx " "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | " - "kind=%#02x APT=%-6s %c%c%c%c%c", + "kind=%#02x APT=%-6s %c%c%c%c", vm->name, (sgt != NULL) ? "MAP" : "UNMAP", virt_addr, @@ -727,7 +727,6 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm, attrs->cacheable ? 'C' : '-', attrs->sparse ? 'S' : '-', attrs->priv ? 'P' : '-', - attrs->coherent ? 'I' : '-', attrs->valid ? 'V' : '-'); err = __nvgpu_gmmu_do_update_page_table(vm, @@ -785,7 +784,6 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, .rw_flag = rw_flag, .sparse = sparse, .priv = priv, - .coherent = flags & NVGPU_VM_MAP_IO_COHERENT, .valid = (flags & NVGPU_VM_MAP_UNMAPPED_PTE) == 0U, .aperture = aperture }; @@ -801,14 +799,6 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, attrs.l3_alloc = (bool)(flags & NVGPU_VM_MAP_L3_ALLOC); - /* - * Handle the IO coherency aperture: make sure the .aperture field is - * correct based on the IO coherency flag. - */ - if (attrs.coherent && attrs.aperture == APERTURE_SYSMEM) { - attrs.aperture = APERTURE_SYSMEM_COH; - } - /* * Only allocate a new GPU VA range if we haven't already been passed a * GPU VA range. This facilitates fixed mappings. @@ -866,7 +856,6 @@ void gk20a_locked_gmmu_unmap(struct vm_gk20a *vm, .rw_flag = rw_flag, .sparse = sparse, .priv = 0, - .coherent = 0, .valid = 0, .aperture = APERTURE_INVALID, }; diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 7ca07fc6b..d6ca478a7 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -288,7 +288,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm, pte_dbg(g, attrs, "PTE: i=%-4u size=%-2u offs=%-4u | " "GPU %#-12llx phys %#-12llx " - "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c%c " + "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c " "ctag=0x%08x " "[0x%08x, 0x%08x]", pd_idx, l->entry_size, pd_offset, @@ -300,7 +300,6 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm, attrs->cacheable ? 'C' : '-', attrs->sparse ? 'S' : '-', attrs->priv ? 'P' : '-', - attrs->coherent ? 'I' : '-', attrs->valid ? 'V' : '-', U32(attrs->ctag) >> U32(ctag_shift), pte_w[1], pte_w[0]); diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 043d4a7f2..080e899c8 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -254,7 +254,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm, "vm=%s " "PTE: i=%-4u size=%-2u | " "GPU %#-12llx phys %#-12llx " - "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c%c " + "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c " "ctag=0x%08x " "[0x%08x, 0x%08x]", vm->name, @@ -267,7 +267,6 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm, attrs->cacheable ? 'C' : '-', attrs->sparse ? 'S' : '-', attrs->priv ? 'P' : '-', - attrs->coherent ? 'I' : '-', attrs->valid ? 'V' : '-', (u32)attrs->ctag / g->ops.fb.compression_page_size(g), pte_w[1], pte_w[0]); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h index d7db66fd4..3ad0b80da 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -63,7 +63,6 @@ enum gk20a_mem_rw_flag { * rw_flag: Flag from enum gk20a_mem_rw_flag * sparse: Set if the mapping should be sparse. * priv: Privilidged mapping. - * coherent: Set if the mapping should be IO coherent. * valid: Set if the PTE should be marked valid. * aperture: VIDMEM or SYSMEM. * debug: When set print debugging info. @@ -81,7 +80,6 @@ struct nvgpu_gmmu_attrs { enum gk20a_mem_rw_flag rw_flag; bool sparse; bool priv; - bool coherent; bool valid; enum nvgpu_aperture aperture; bool debug; diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 51efd8f17..d6e830eb9 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h @@ -1954,6 +1954,8 @@ struct nvgpu_as_bind_channel_args { * * Specify that a mapping shall be IO coherent. * + * DEPRECATED: do not use! This will be removed in a future update. + * * %NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE * * Specify that a mapping shall be marked as invalid but otherwise