From 4e1d8519c8e4bd9ce7b72eff20618f74ee9a29e2 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 5 Aug 2019 12:02:45 +0530 Subject: [PATCH] gpu: nvgpu: Deleting falcon's unit gp106 & gv100 support -Deleting GP106 & GV100 from falcon unit as GP106 & GV100 is not supported anymore. JIRA NVGPU-3243 Change-Id: I931ca7b3cc5d165ff1d2bbfa251079c1d4ecec66 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/2168083 Reviewed-by: mobile promotions Tested-by: mobile promotions --- arch/nvgpu-common.yaml | 6 +- drivers/gpu/nvgpu/Makefile | 2 - drivers/gpu/nvgpu/Makefile.sources | 2 - drivers/gpu/nvgpu/common/falcon/falcon.c | 4 - .../gpu/nvgpu/common/falcon/falcon_sw_gp106.c | 90 ------------------- .../gpu/nvgpu/common/falcon/falcon_sw_gp106.h | 28 ------ .../gpu/nvgpu/common/falcon/falcon_sw_gv100.c | 78 ---------------- .../gpu/nvgpu/common/falcon/falcon_sw_gv100.h | 28 ------ .../gpu/nvgpu/common/falcon/falcon_sw_tu104.c | 16 +++- 9 files changed, 15 insertions(+), 239 deletions(-) delete mode 100644 drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.c delete mode 100644 drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.h delete mode 100644 drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.c delete mode 100644 drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.h diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 96c418d8e..fae1ae6f4 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -285,11 +285,7 @@ falcon: owner: Sagar K safe: no gpu: dgpu - sources: [ common/falcon/falcon_sw_gp106.c, - common/falcon/falcon_sw_gv100.c, - common/falcon/falcon_sw_tu104.c, - common/falcon/falcon_sw_gp106.h, - common/falcon/falcon_sw_gv100.h, + sources: [ common/falcon/falcon_sw_tu104.c, common/falcon/falcon_sw_tu104.h ] deps: [ ] tags: diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 990204ce3..5719d4a82 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -472,8 +472,6 @@ nvgpu-y += \ common/vbios/bios_sw_tu104.o \ common/falcon/falcon.o \ common/falcon/falcon_sw_gk20a.o \ - common/falcon/falcon_sw_gp106.o \ - common/falcon/falcon_sw_gv100.o \ common/falcon/falcon_sw_tu104.o \ common/engine_queues/engine_mem_queue.o \ common/engine_queues/engine_dmem_queue.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index a684860b9..ca6504e3b 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -571,8 +571,6 @@ srcs += common/sec2/sec2.c \ common/vbios/bios.c \ common/vbios/bios_sw_gv100.c \ common/vbios/bios_sw_tu104.c \ - common/falcon/falcon_sw_gp106.c \ - common/falcon/falcon_sw_gv100.c \ common/falcon/falcon_sw_tu104.c \ common/acr/acr_sw_tu104.c \ common/mm/allocators/page_allocator.c \ diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index dd4a2b3d3..8d19a2255 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -26,7 +26,6 @@ #include "falcon_sw_gk20a.h" #ifdef CONFIG_NVGPU_DGPU -#include "falcon_sw_gv100.h" #include "falcon_sw_tu104.h" #endif @@ -448,9 +447,6 @@ static int falcon_sw_init(struct gk20a *g, struct nvgpu_falcon *flcn) gk20a_falcon_sw_init(flcn); break; #ifdef CONFIG_NVGPU_DGPU - case NVGPU_GPUID_GV100: - gv100_falcon_sw_init(flcn); - break; case NVGPU_GPUID_TU104: tu104_falcon_sw_init(flcn); break; diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.c b/drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.c deleted file mode 100644 index 79d073ea4..000000000 --- a/drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#include -#include - -#include "falcon_sw_gk20a.h" -#include "falcon_sw_gp106.h" - -void gp106_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) -{ - struct gk20a *g = flcn->g; - struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = - &flcn->flcn_engine_dep_ops; - - gk20a_falcon_engine_dependency_ops(flcn); - - switch (flcn->flcn_id) { - case FALCON_ID_PMU: - flcn_eng_dep_ops->reset_eng = g->ops.pmu.pmu_reset; - break; - case FALCON_ID_SEC2: - flcn_eng_dep_ops->reset_eng = g->ops.sec2.sec2_reset; - break; - default: - flcn_eng_dep_ops->reset_eng = NULL; - break; - } -} - -void gp106_falcon_sw_init(struct nvgpu_falcon *flcn) -{ - struct gk20a *g = flcn->g; - - switch (flcn->flcn_id) { - case FALCON_ID_PMU: - flcn->flcn_base = g->ops.pmu.falcon_base_addr(); - flcn->is_falcon_supported = true; - flcn->is_interrupt_enabled = true; - break; - case FALCON_ID_SEC2: - flcn->flcn_base = g->ops.sec2.falcon_base_addr(); - flcn->is_falcon_supported = true; - flcn->is_interrupt_enabled = false; - break; - case FALCON_ID_FECS: - flcn->flcn_base = g->ops.gr.falcon.fecs_base_addr(); - flcn->is_falcon_supported = true; - flcn->is_interrupt_enabled = false; - break; - case FALCON_ID_GPCCS: - flcn->flcn_base = g->ops.gr.falcon.gpccs_base_addr(); - flcn->is_falcon_supported = true; - flcn->is_interrupt_enabled = false; - break; - case FALCON_ID_NVDEC: - flcn->flcn_base = g->ops.nvdec.falcon_base_addr(); - flcn->is_falcon_supported = true; - flcn->is_interrupt_enabled = true; - break; - default: - flcn->is_falcon_supported = false; - break; - } - - if (flcn->is_falcon_supported) { - gp106_falcon_engine_dependency_ops(flcn); - } else { - nvgpu_info(g, "falcon 0x%x not supported on %s", - flcn->flcn_id, g->name); - } -} diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.h b/drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.h deleted file mode 100644 index 9321ce92d..000000000 --- a/drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_FALCON_SW_GP106_H -#define NVGPU_FALCON_SW_GP106_H - -void gp106_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn); -void gp106_falcon_sw_init(struct nvgpu_falcon *flcn); - -#endif /* NVGPU_FALCON_SW_GP106_H */ diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.c b/drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.c deleted file mode 100644 index a4c6cc121..000000000 --- a/drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#include -#include - -#include "falcon_sw_gk20a.h" -#include "falcon_sw_gp106.h" -#include "falcon_sw_gv100.h" - -void gv100_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) -{ - struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = - &flcn->flcn_engine_dep_ops; - struct gk20a *g = flcn->g; - - gk20a_falcon_engine_dependency_ops(flcn); - - switch (flcn->flcn_id) { - case FALCON_ID_GSPLITE: - flcn_eng_dep_ops->reset_eng = g->ops.gsp.gsp_reset; - break; - default: - flcn_eng_dep_ops->reset_eng = NULL; - break; - } -} - -void gv100_falcon_sw_init(struct nvgpu_falcon *flcn) -{ - struct gk20a *g = flcn->g; - - switch (flcn->flcn_id) { - case FALCON_ID_MINION: - flcn->flcn_base = g->ops.nvlink.minion.base_addr(g); - flcn->is_falcon_supported = true; - flcn->is_interrupt_enabled = true; - break; - case FALCON_ID_GSPLITE: - flcn->flcn_base = g->ops.gsp.falcon_base_addr(); - flcn->is_falcon_supported = true; - flcn->is_interrupt_enabled = false; - break; - default: - flcn->is_falcon_supported = false; - break; - } - - if (flcn->is_falcon_supported) { - gv100_falcon_engine_dependency_ops(flcn); - } else { - /* - * Forward call to previous chip's SW init - * to fetch info for requested - * falcon as no changes between - * current & previous chips. - */ - gp106_falcon_sw_init(flcn); - } -} diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.h b/drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.h deleted file mode 100644 index 43d8020e0..000000000 --- a/drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_FALCON_SW_GV100_H -#define NVGPU_FALCON_SW_GV100_H - -void gv100_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn); -void gv100_falcon_sw_init(struct nvgpu_falcon *flcn); - -#endif /* NVGPU_FALCON_SW_GV100_H */ diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_tu104.c b/drivers/gpu/nvgpu/common/falcon/falcon_sw_tu104.c index f98fff78a..217a1d082 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_sw_tu104.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_sw_tu104.c @@ -23,7 +23,6 @@ #include #include "falcon_sw_gk20a.h" -#include "falcon_sw_gv100.h" #include "falcon_sw_tu104.h" void tu104_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) @@ -35,6 +34,9 @@ void tu104_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) gk20a_falcon_engine_dependency_ops(flcn); switch (flcn->flcn_id) { + case FALCON_ID_GSPLITE: + flcn_eng_dep_ops->reset_eng = g->ops.gsp.gsp_reset; + break; case FALCON_ID_SEC2: flcn_eng_dep_ops->reset_eng = g->ops.sec2.sec2_reset; flcn_eng_dep_ops->copy_to_emem = g->ops.sec2.sec2_copy_to_emem; @@ -52,12 +54,22 @@ void tu104_falcon_sw_init(struct nvgpu_falcon *flcn) struct gk20a *g = flcn->g; switch (flcn->flcn_id) { + case FALCON_ID_GSPLITE: + flcn->flcn_base = g->ops.gsp.falcon_base_addr(); + flcn->is_falcon_supported = true; + flcn->is_interrupt_enabled = false; + break; case FALCON_ID_SEC2: flcn->flcn_base = g->ops.sec2.falcon_base_addr(); flcn->is_falcon_supported = true; flcn->is_interrupt_enabled = true; flcn->emem_supported = true; break; + case FALCON_ID_MINION: + flcn->flcn_base = g->ops.nvlink.minion.base_addr(g); + flcn->is_falcon_supported = true; + flcn->is_interrupt_enabled = true; + break; case FALCON_ID_NVDEC: flcn->flcn_base = g->ops.nvdec.falcon_base_addr(); flcn->is_falcon_supported = true; @@ -81,6 +93,6 @@ void tu104_falcon_sw_init(struct nvgpu_falcon *flcn) * falcon as no changes between * current & previous chips. */ - gv100_falcon_sw_init(flcn); + gk20a_falcon_sw_init(flcn); } }