From 4e9534c24373e9bb18fa3cce8126258cb0ed56e3 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 3 May 2019 17:30:51 -0700 Subject: [PATCH] gpu: nvgpu: add helper function for fecs dmem data Added helper function gm20b_gr_falcon_update_fecs_dmem_data programming fecs dmem data. With using this helper function, avoid repeating same code twice. JIRA NVGPU-3226 Change-Id: I490cc6b5ed6a1df5bcd0590833c8f9b83661d538 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2111750 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 57 ++++++++----------- 1 file changed, 23 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index 0d47f0a43..129dbf0cb 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -317,6 +317,25 @@ void gm20b_gr_falcon_bind_instblk(struct gk20a *g, } +static void gm20b_gr_falcon_program_fecs_dmem_data(struct gk20a *g, + u32 reg_offset, u32 addr_code32, u32 addr_data32, + u32 code_size, u32 data_size) +{ + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 4); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), addr_code32); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), code_size); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), addr_data32); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), data_size); +} + void gm20b_gr_falcon_load_ctxsw_ucode_header(struct gk20a *g, u32 reg_offset, u32 boot_signature, u32 addr_code32, u32 addr_data32, u32 code_size, u32 data_size) @@ -347,46 +366,16 @@ void gm20b_gr_falcon_load_ctxsw_ucode_header(struct gk20a *g, nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 4); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), - addr_code32); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), - code_size); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), - addr_data32); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), - data_size); + gm20b_gr_falcon_program_fecs_dmem_data(g, reg_offset, + addr_code32, addr_data32, code_size, data_size); break; case FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED: case FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED: case FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED: case FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED2: case FALCON_UCODE_SIG_T21X_GPCCS_WITHOUT_RESERVED: - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 4); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), - addr_code32); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), - code_size); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), - addr_data32); - nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), - data_size); + gm20b_gr_falcon_program_fecs_dmem_data(g, reg_offset, + addr_code32, addr_data32, code_size, data_size); break; case FALCON_UCODE_SIG_T12X_FECS_OLDER: case FALCON_UCODE_SIG_T12X_GPCCS_OLDER: