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gpu: nvgpu: update tpc-pg support
- Add tpc count variable in the platform struct
to store the number of tpcs present in the chip.
This count is needed before GPU boots to provide
support for static TPC-PG feature.
- Remove valid_tpc_pg_mask and valid_gpc_fbp_pg_mask
variable from gk20a struct as it is already taken care
in platform struct.
Bug 3765637
JIRA NVGPU-8210
Change-Id: Ic04af4b7c24f5e790c52708c117e45a3bb0d1810
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2725960
(cherry picked from commit 001e9a2695)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2775710
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
@@ -783,15 +783,6 @@ struct gk20a {
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bool can_tpc_pg;
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bool can_tpc_pg;
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bool can_fbp_pg;
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bool can_fbp_pg;
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bool can_gpc_pg;
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bool can_gpc_pg;
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/*
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* Valid config array for tpc pg mask
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* and gpc/fbp mask. These valid values
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* are chip specific and calculated based
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* on available number of GPC, FBP and TPC
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*/
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u32 valid_tpc_pg_mask[MAX_PG_TPC_CONFIGS];
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u32 valid_gpc_fbp_pg_mask[MAX_PG_GPC_FBP_CONFIGS];
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#endif
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#endif
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#ifdef CONFIG_NVGPU_DGPU
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#ifdef CONFIG_NVGPU_DGPU
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@@ -182,7 +182,6 @@ static void nvgpu_init_timeslice(struct gk20a *g)
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static void nvgpu_init_pm_vars(struct gk20a *g)
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static void nvgpu_init_pm_vars(struct gk20a *g)
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{
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{
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struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
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struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
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u32 i = 0;
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/*
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/*
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* Set up initial power settings. For non-slicon platforms, disable
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* Set up initial power settings. For non-slicon platforms, disable
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@@ -231,12 +230,6 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
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g->can_tpc_pg = platform->can_tpc_pg;
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g->can_tpc_pg = platform->can_tpc_pg;
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g->can_gpc_pg = platform->can_gpc_pg;
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g->can_gpc_pg = platform->can_gpc_pg;
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g->can_fbp_pg = platform->can_fbp_pg;
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g->can_fbp_pg = platform->can_fbp_pg;
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for (i = 0; i < MAX_PG_TPC_CONFIGS; i++)
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g->valid_tpc_pg_mask[i] = platform->valid_tpc_pg_mask[i];
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for (i = 0; i < MAX_PG_GPC_FBP_CONFIGS; i++)
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g->valid_gpc_fbp_pg_mask[i] = platform->valid_gpc_fbp_pg_mask[i];
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#endif
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#endif
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g->ldiv_slowdown_factor = platform->ldiv_slowdown_factor_init;
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g->ldiv_slowdown_factor = platform->ldiv_slowdown_factor_init;
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/* if default delay is not set, set default delay to 500msec */
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/* if default delay is not set, set default delay to 500msec */
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@@ -126,6 +126,9 @@ struct gk20a_platform {
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/* Valid GPC-PG and FBP-PG mask */
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/* Valid GPC-PG and FBP-PG mask */
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u32 valid_gpc_fbp_pg_mask[MAX_PG_GPC_FBP_CONFIGS];
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u32 valid_gpc_fbp_pg_mask[MAX_PG_GPC_FBP_CONFIGS];
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/* available TPC count in a chip */
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u32 tpc_count;
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#endif
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#endif
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/* Delay before rail gated */
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/* Delay before rail gated */
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int railgate_delay_init;
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int railgate_delay_init;
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@@ -1077,7 +1077,7 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
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!= 0) {
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!= 0) {
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nvgpu_err(g, "golden image size already initialized");
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nvgpu_err(g, "golden image size already initialized");
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nvgpu_mutex_release(&g->static_pg_lock);
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nvgpu_mutex_release(&g->static_pg_lock);
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return -ENODEV;
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return -EINVAL;
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}
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}
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if (platform->set_tpc_pg_mask != NULL) {
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if (platform->set_tpc_pg_mask != NULL) {
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