From 4edf952e3e5fcff453ce2bcc0f4d1e709c771816 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 6 Jul 2021 12:45:58 +0530 Subject: [PATCH] gpu: nvgpu: fix rule 5.1 misra violations in common.gr Fix rule 5.1 misra violations in common.gr by renaming below functions : nvgpu_gr_config_get_gpc_tpc_mask_base -> nvgpu_gr_config_get_base_mask_gpc_tpc nvgpu_gr_config_get_gpc_tpc_count_base -> nvgpu_gr_config_get_base_count_gpc_tpc gm20b_ctxsw_prog_set_priv_access_map_config_mode -> gm20b_ctxsw_prog_set_config_mode_priv_access_map gm20b_ctxsw_prog_set_priv_access_map_addr -> gm20b_ctxsw_prog_set_addr_priv_access_map gm20b_gr_falcon_read_fecs_ctxsw_mailbox -> gm20b_gr_falcon_read_mailbox_fecs_ctxsw gm20b_gr_falcon_read_fecs_ctxsw_status0 -> gm20b_gr_falcon_read_status0_fecs_ctxsw gm20b_gr_falcon_read_fecs_ctxsw_status1 -> gm20b_gr_falcon_read_status1_fecs_ctxsw gv11b_gr_intr_get_sm_hww_warp_esr_pc -> gv11b_gr_intr_get_warp_esr_pc_sm_hww gv11b_gr_intr_get_sm_hww_warp_esr -> gv11b_gr_intr_get_warp_esr_sm_hww Jira NVGPU-6779 Change-Id: Icbe23a7b022373785968fc417ee247e2d80cfcc6 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554521 (cherry picked from commit 1432650774506f2a7e45f70b084f498736d0d0c5) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555330 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr_config.c | 4 ++-- .../gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h | 6 +++--- .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c | 4 ++-- drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h | 8 ++++---- .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c | 6 +++--- drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c | 2 +- drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c | 2 +- drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c | 2 +- drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c | 2 +- drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c | 2 +- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h | 6 +++--- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c | 4 ++-- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 14 +++++++------- drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 14 +++++++------- drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 10 +++++----- drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 10 +++++----- drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 14 +++++++------- drivers/gpu/nvgpu/hal/init/hal_tu104.c | 14 +++++++------- drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c | 4 ++-- drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c | 4 ++-- drivers/gpu/nvgpu/include/nvgpu/gr/config.h | 4 ++-- drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 2 +- drivers/gpu/nvgpu/os/linux/sysfs.c | 2 +- libs/dgpu/libnvgpu-drv-dgpu_safe.export | 4 ++-- libs/igpu/libnvgpu-drv-igpu_safe.export | 4 ++-- userspace/units/gr/config/nvgpu-gr-config.c | 4 ++-- userspace/units/gr/config/nvgpu-gr-config.h | 6 +++--- userspace/units/gr/intr/nvgpu-gr-intr.h | 14 +++++++------- userspace/units/gr/setup/nvgpu-gr-setup.h | 4 ++-- 29 files changed, 88 insertions(+), 88 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr_config.c b/drivers/gpu/nvgpu/common/gr/gr_config.c index 5fd6d0a2b..2b3ccdb63 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_config.c +++ b/drivers/gpu/nvgpu/common/gr/gr_config.c @@ -732,7 +732,7 @@ u32 nvgpu_gr_config_get_gpc_ppc_count(struct nvgpu_gr_config *config, return config->gpc_ppc_count[gpc_index]; } -u32 *nvgpu_gr_config_get_gpc_tpc_count_base(struct nvgpu_gr_config *config) +u32 *nvgpu_gr_config_get_base_count_gpc_tpc(struct nvgpu_gr_config *config) { return config->gpc_tpc_count; } @@ -754,7 +754,7 @@ u32 nvgpu_gr_config_get_pes_tpc_count(struct nvgpu_gr_config *config, return config->pes_tpc_count[pes_index][gpc_index]; } -u32 *nvgpu_gr_config_get_gpc_tpc_mask_base(struct nvgpu_gr_config *config) +u32 *nvgpu_gr_config_get_base_mask_gpc_tpc(struct nvgpu_gr_config *config) { return config->gpc_tpc_mask; } diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h index 351af3441..dc55f15af 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -36,9 +36,9 @@ void gm20b_ctxsw_prog_set_patch_addr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *ctx_mem); -void gm20b_ctxsw_prog_set_priv_access_map_config_mode(struct gk20a *g, +void gm20b_ctxsw_prog_set_config_mode_priv_access_map(struct gk20a *g, struct nvgpu_mem *ctx_mem, bool allow_all); -void gm20b_ctxsw_prog_set_priv_access_map_addr(struct gk20a *g, +void gm20b_ctxsw_prog_set_addr_priv_access_map(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, struct nvgpu_mem *ctx_mem); diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c index 89debb824..e89acf2c5 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c @@ -63,7 +63,7 @@ void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, ctxsw_prog_main_image_num_restore_ops_o(), 0); } -void gm20b_ctxsw_prog_set_priv_access_map_config_mode(struct gk20a *g, +void gm20b_ctxsw_prog_set_config_mode_priv_access_map(struct gk20a *g, struct nvgpu_mem *ctx_mem, bool allow_all) { if (allow_all) { @@ -77,7 +77,7 @@ void gm20b_ctxsw_prog_set_priv_access_map_config_mode(struct gk20a *g, } } -void gm20b_ctxsw_prog_set_priv_access_map_addr(struct gk20a *g, +void gm20b_ctxsw_prog_set_addr_priv_access_map(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr) { nvgpu_mem_wr(g, ctx_mem, diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h index 7a67dc37d..7411a3f7b 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -32,7 +32,7 @@ struct nvgpu_gr_falcon_query_sizes; void gm20b_gr_falcon_fecs_ctxsw_clear_mailbox(struct gk20a *g, u32 reg_index, u32 clear_val); -u32 gm20b_gr_falcon_read_fecs_ctxsw_mailbox(struct gk20a *g, u32 reg_index); +u32 gm20b_gr_falcon_read_mailbox_fecs_ctxsw(struct gk20a *g, u32 reg_index); void gm20b_gr_falcon_fecs_host_clear_intr(struct gk20a *g, u32 fecs_intr); u32 gm20b_gr_falcon_fecs_host_intr_status(struct gk20a *g, struct nvgpu_fecs_host_intr_status *fecs_host_intr); @@ -59,8 +59,8 @@ u32 gm20b_gr_falcon_get_fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block); int gm20b_gr_falcon_init_ctx_state(struct gk20a *g, struct nvgpu_gr_falcon_query_sizes *sizes); -u32 gm20b_gr_falcon_read_fecs_ctxsw_status0(struct gk20a *g); -u32 gm20b_gr_falcon_read_fecs_ctxsw_status1(struct gk20a *g); +u32 gm20b_gr_falcon_read_status0_fecs_ctxsw(struct gk20a *g); +u32 gm20b_gr_falcon_read_status1_fecs_ctxsw(struct gk20a *g); #ifdef CONFIG_NVGPU_GRAPHICS int gm20b_gr_falcon_submit_fecs_sideband_method_op(struct gk20a *g, struct nvgpu_fecs_method_op op); diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c index c50ae6a05..500c7841b 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c @@ -878,7 +878,7 @@ u32 gm20b_gr_falcon_get_fecs_current_ctx_data(struct gk20a *g, gr_fecs_current_ctx_valid_f(1); } -u32 gm20b_gr_falcon_read_fecs_ctxsw_mailbox(struct gk20a *g, u32 reg_index) +u32 gm20b_gr_falcon_read_mailbox_fecs_ctxsw(struct gk20a *g, u32 reg_index) { return nvgpu_readl(g, gr_fecs_ctxsw_mailbox_r(reg_index)); } @@ -943,12 +943,12 @@ u32 gm20b_gr_falcon_fecs_host_intr_status(struct gk20a *g, return gr_fecs_intr; } -u32 gm20b_gr_falcon_read_fecs_ctxsw_status0(struct gk20a *g) +u32 gm20b_gr_falcon_read_status0_fecs_ctxsw(struct gk20a *g) { return nvgpu_readl(g, gr_fecs_ctxsw_status_fe_0_r()); } -u32 gm20b_gr_falcon_read_fecs_ctxsw_status1(struct gk20a *g) +u32 gm20b_gr_falcon_read_status1_fecs_ctxsw(struct gk20a *g) { return nvgpu_readl(g, gr_fecs_ctxsw_status_1_r()); } diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c index e736e3b79..85c51126d 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c @@ -158,7 +158,7 @@ static void gr_ga100_dump_tpc_activity_regs(struct gk20a *g, u32 reg_index = 0U, offset = 0U; u32 i = 0U; - if (nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) == NULL) { + if (nvgpu_gr_config_get_base_count_gpc_tpc(gr->config) == NULL) { return; } diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c index 89e604a1f..816606e74 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c @@ -163,7 +163,7 @@ static void gr_ga10b_dump_tpc_activity_regs(struct gk20a *g, u32 reg_index = 0U, offset = 0U; u32 i = 0U; - if (nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) == NULL) { + if (nvgpu_gr_config_get_base_count_gpc_tpc(gr->config) == NULL) { return; } diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c index a85bdcce6..8c7ff7cd0 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c @@ -288,7 +288,7 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g, gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x", gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); - if ((nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) != NULL) && + if ((nvgpu_gr_config_get_base_count_gpc_tpc(gr->config) != NULL) && (nvgpu_gr_config_get_gpc_tpc_count(gr->config, 0) == 2U)) { gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x", diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c index 8b27331cf..3355162c2 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c @@ -283,7 +283,7 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g, gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x", gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); - if ((nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) != NULL) && + if ((nvgpu_gr_config_get_base_count_gpc_tpc(gr->config) != NULL) && (nvgpu_gr_config_get_gpc_tpc_count(gr->config, 0) == 2U)) { gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x", diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c index 34a18b976..11f3cec05 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c @@ -323,7 +323,7 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g, gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x", gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); - if ((nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) != NULL) && + if ((nvgpu_gr_config_get_base_count_gpc_tpc(gr->config) != NULL) && (nvgpu_gr_config_get_gpc_tpc_count(gr->config, 0) == 2U)) { gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x", diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h index 60a3abddc..78405d23a 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -132,12 +132,12 @@ void gv11b_gr_intr_handle_ssync_hww(struct gk20a *g, u32 *ssync_esr); u32 gv11b_gr_intr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, struct nvgpu_channel *fault_ch); -u32 gv11b_gr_intr_get_sm_hww_warp_esr(struct gk20a *g, +u32 gv11b_gr_intr_get_warp_esr_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm); u32 gv11b_gr_intr_get_sm_hww_global_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm); u32 gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); -u64 gv11b_gr_intr_get_sm_hww_warp_esr_pc(struct gk20a *g, u32 offset); +u64 gv11b_gr_intr_get_warp_esr_pc_sm_hww(struct gk20a *g, u32 offset); u32 gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val(void); diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c index 70e076c9f..a34906c03 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c @@ -1943,7 +1943,7 @@ record_fail: return sm_id; } -u32 gv11b_gr_intr_get_sm_hww_warp_esr(struct gk20a *g, +u32 gv11b_gr_intr_get_warp_esr_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm) { u32 offset = nvgpu_safe_add_u32(nvgpu_gr_gpc_offset(g, gpc), @@ -1985,7 +1985,7 @@ u32 gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) return global_esr_mask; } -u64 gv11b_gr_intr_get_sm_hww_warp_esr_pc(struct gk20a *g, u32 offset) +u64 gv11b_gr_intr_get_warp_esr_pc_sm_hww(struct gk20a *g, u32 offset) { u64 hww_warp_esr_pc; u32 addr_hi = nvgpu_readl(g, nvgpu_safe_add_u32( diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 14c2c59b4..fb1468765 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -445,8 +445,8 @@ static const struct gops_gr_ctxsw_prog ga100_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, + .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, + .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, @@ -707,8 +707,8 @@ static const struct gops_gr_intr ga100_ops_gr_intr = { .handle_ssync_hww = gv11b_gr_intr_handle_ssync_hww, .log_mme_exception = tu104_gr_intr_log_mme_exception, .record_sm_error_state = gv11b_gr_intr_record_sm_error_state, - .get_sm_hww_warp_esr = gv11b_gr_intr_get_sm_hww_warp_esr, - .get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_sm_hww_warp_esr_pc, + .get_sm_hww_warp_esr = gv11b_gr_intr_get_warp_esr_sm_hww, + .get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_warp_esr_pc_sm_hww, .get_sm_hww_global_esr = gv11b_gr_intr_get_sm_hww_global_esr, .get_sm_no_lock_down_hww_global_esr_mask = gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask, .get_ctxsw_checksum_mismatch_mailbox_val = gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val, @@ -726,7 +726,7 @@ static const struct gops_gr_intr ga100_ops_gr_intr = { static const struct gops_gr_falcon ga100_ops_gr_falcon = { .handle_fecs_ecc_error = gv11b_gr_falcon_handle_fecs_ecc_error, - .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_fecs_ctxsw_mailbox, + .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_mailbox_fecs_ctxsw, .fecs_host_clear_intr = gm20b_gr_falcon_fecs_host_clear_intr, .fecs_host_intr_status = gm20b_gr_falcon_fecs_host_intr_status, .fecs_base_addr = gm20b_gr_falcon_fecs_base_addr, @@ -748,8 +748,8 @@ static const struct gops_gr_falcon ga100_ops_gr_falcon = { .get_fecs_current_ctx_data = gm20b_gr_falcon_get_fecs_current_ctx_data, .init_ctx_state = gp10b_gr_falcon_init_ctx_state, .fecs_host_int_enable = gv11b_gr_falcon_fecs_host_int_enable, - .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_fecs_ctxsw_status0, - .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_fecs_ctxsw_status1, + .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_status0_fecs_ctxsw, + .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_status1_fecs_ctxsw, .load_ctxsw_ucode = nvgpu_gr_falcon_load_secure_ctxsw_ucode, #ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT .load_ctxsw_ucode_header = gm20b_gr_falcon_load_ctxsw_ucode_header, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 60be8a1e3..d2583c69b 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -408,8 +408,8 @@ static const struct gops_gr_ctxsw_prog ga10b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, + .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, + .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, @@ -685,8 +685,8 @@ static const struct gops_gr_intr ga10b_ops_gr_intr = { .clear_sm_hww = gv11b_gr_intr_clear_sm_hww, .handle_ssync_hww = gv11b_gr_intr_handle_ssync_hww, .record_sm_error_state = gv11b_gr_intr_record_sm_error_state, - .get_sm_hww_warp_esr = gv11b_gr_intr_get_sm_hww_warp_esr, - .get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_sm_hww_warp_esr_pc, + .get_sm_hww_warp_esr = gv11b_gr_intr_get_warp_esr_sm_hww, + .get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_warp_esr_pc_sm_hww, .get_sm_hww_global_esr = gv11b_gr_intr_get_sm_hww_global_esr, .get_sm_no_lock_down_hww_global_esr_mask = gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask, .get_ctxsw_checksum_mismatch_mailbox_val = gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val, @@ -704,7 +704,7 @@ static const struct gops_gr_intr ga10b_ops_gr_intr = { static const struct gops_gr_falcon ga10b_ops_gr_falcon = { .handle_fecs_ecc_error = gv11b_gr_falcon_handle_fecs_ecc_error, - .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_fecs_ctxsw_mailbox, + .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_mailbox_fecs_ctxsw, .fecs_host_clear_intr = gm20b_gr_falcon_fecs_host_clear_intr, .fecs_host_intr_status = gm20b_gr_falcon_fecs_host_intr_status, .fecs_base_addr = gm20b_gr_falcon_fecs_base_addr, @@ -726,8 +726,8 @@ static const struct gops_gr_falcon ga10b_ops_gr_falcon = { .get_fecs_current_ctx_data = gm20b_gr_falcon_get_fecs_current_ctx_data, .init_ctx_state = gp10b_gr_falcon_init_ctx_state, .fecs_host_int_enable = gv11b_gr_falcon_fecs_host_int_enable, - .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_fecs_ctxsw_status0, - .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_fecs_ctxsw_status1, + .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_status0_fecs_ctxsw, + .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_status1_fecs_ctxsw, #ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT .load_ctxsw_ucode_header = gm20b_gr_falcon_load_ctxsw_ucode_header, .load_ctxsw_ucode_boot = gm20b_gr_falcon_load_ctxsw_ucode_boot, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 7861f2c09..9ba7ec949 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -201,8 +201,8 @@ static const struct gops_gr_ctxsw_prog gm20b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gm20b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gm20b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, + .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, + .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, @@ -401,7 +401,7 @@ static const struct gops_gr_intr gm20b_ops_gr_intr = { }; static const struct gops_gr_falcon gm20b_ops_gr_falcon = { - .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_fecs_ctxsw_mailbox, + .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_mailbox_fecs_ctxsw, .fecs_host_clear_intr = gm20b_gr_falcon_fecs_host_clear_intr, .fecs_host_intr_status = gm20b_gr_falcon_fecs_host_intr_status, .fecs_base_addr = gm20b_gr_falcon_fecs_base_addr, @@ -423,8 +423,8 @@ static const struct gops_gr_falcon gm20b_ops_gr_falcon = { .get_fecs_current_ctx_data = gm20b_gr_falcon_get_fecs_current_ctx_data, .init_ctx_state = gm20b_gr_falcon_init_ctx_state, .fecs_host_int_enable = gm20b_gr_falcon_fecs_host_int_enable, - .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_fecs_ctxsw_status0, - .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_fecs_ctxsw_status1, + .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_status0_fecs_ctxsw, + .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_status1_fecs_ctxsw, #ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT .load_ctxsw_ucode_header = gm20b_gr_falcon_load_ctxsw_ucode_header, .load_ctxsw_ucode_boot = gm20b_gr_falcon_load_ctxsw_ucode_boot, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 4360a04b7..cac77362f 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -255,8 +255,8 @@ static const struct gops_gr_ctxsw_prog gp10b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, + .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, + .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, @@ -478,7 +478,7 @@ static const struct gops_gr_intr gp10b_ops_gr_intr = { }; static const struct gops_gr_falcon gp10b_ops_gr_falcon = { - .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_fecs_ctxsw_mailbox, + .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_mailbox_fecs_ctxsw, .fecs_host_clear_intr = gm20b_gr_falcon_fecs_host_clear_intr, .fecs_host_intr_status = gm20b_gr_falcon_fecs_host_intr_status, .fecs_base_addr = gm20b_gr_falcon_fecs_base_addr, @@ -500,8 +500,8 @@ static const struct gops_gr_falcon gp10b_ops_gr_falcon = { .get_fecs_current_ctx_data = gm20b_gr_falcon_get_fecs_current_ctx_data, .init_ctx_state = gp10b_gr_falcon_init_ctx_state, .fecs_host_int_enable = gm20b_gr_falcon_fecs_host_int_enable, - .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_fecs_ctxsw_status0, - .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_fecs_ctxsw_status1, + .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_status0_fecs_ctxsw, + .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_status1_fecs_ctxsw, #ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT .load_ctxsw_ucode_header = gm20b_gr_falcon_load_ctxsw_ucode_header, .load_ctxsw_ucode_boot = gm20b_gr_falcon_load_ctxsw_ucode_boot, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index c0c8e960a..0a64777cb 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -331,8 +331,8 @@ static const struct gops_gr_ctxsw_prog gv11b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, + .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, + .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, @@ -580,8 +580,8 @@ static const struct gops_gr_intr gv11b_ops_gr_intr = { .clear_sm_hww = gv11b_gr_intr_clear_sm_hww, .handle_ssync_hww = gv11b_gr_intr_handle_ssync_hww, .record_sm_error_state = gv11b_gr_intr_record_sm_error_state, - .get_sm_hww_warp_esr = gv11b_gr_intr_get_sm_hww_warp_esr, - .get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_sm_hww_warp_esr_pc, + .get_sm_hww_warp_esr = gv11b_gr_intr_get_warp_esr_sm_hww, + .get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_warp_esr_pc_sm_hww, .get_sm_hww_global_esr = gv11b_gr_intr_get_sm_hww_global_esr, .get_sm_no_lock_down_hww_global_esr_mask = gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask, .get_ctxsw_checksum_mismatch_mailbox_val = gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val, @@ -599,7 +599,7 @@ static const struct gops_gr_intr gv11b_ops_gr_intr = { static const struct gops_gr_falcon gv11b_ops_gr_falcon = { .handle_fecs_ecc_error = gv11b_gr_falcon_handle_fecs_ecc_error, - .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_fecs_ctxsw_mailbox, + .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_mailbox_fecs_ctxsw, .fecs_host_clear_intr = gm20b_gr_falcon_fecs_host_clear_intr, .fecs_host_intr_status = gm20b_gr_falcon_fecs_host_intr_status, .fecs_base_addr = gm20b_gr_falcon_fecs_base_addr, @@ -621,8 +621,8 @@ static const struct gops_gr_falcon gv11b_ops_gr_falcon = { .get_fecs_current_ctx_data = gm20b_gr_falcon_get_fecs_current_ctx_data, .init_ctx_state = gp10b_gr_falcon_init_ctx_state, .fecs_host_int_enable = gv11b_gr_falcon_fecs_host_int_enable, - .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_fecs_ctxsw_status0, - .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_fecs_ctxsw_status1, + .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_status0_fecs_ctxsw, + .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_status1_fecs_ctxsw, #ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT .load_ctxsw_ucode_header = gm20b_gr_falcon_load_ctxsw_ucode_header, .load_ctxsw_ucode_boot = gm20b_gr_falcon_load_ctxsw_ucode_boot, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 3f343881d..4e696d55c 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -376,8 +376,8 @@ static const struct gops_gr_ctxsw_prog tu104_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, + .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, + .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, @@ -624,8 +624,8 @@ static const struct gops_gr_intr tu104_ops_gr_intr = { .handle_ssync_hww = gv11b_gr_intr_handle_ssync_hww, .log_mme_exception = tu104_gr_intr_log_mme_exception, .record_sm_error_state = gv11b_gr_intr_record_sm_error_state, - .get_sm_hww_warp_esr = gv11b_gr_intr_get_sm_hww_warp_esr, - .get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_sm_hww_warp_esr_pc, + .get_sm_hww_warp_esr = gv11b_gr_intr_get_warp_esr_sm_hww, + .get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_warp_esr_pc_sm_hww, .get_sm_hww_global_esr = gv11b_gr_intr_get_sm_hww_global_esr, .get_sm_no_lock_down_hww_global_esr_mask = gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask, .sm_ecc_status_errors = gv11b_gr_intr_sm_ecc_status_errors, @@ -642,7 +642,7 @@ static const struct gops_gr_intr tu104_ops_gr_intr = { static const struct gops_gr_falcon tu104_ops_gr_falcon = { .handle_fecs_ecc_error = gv11b_gr_falcon_handle_fecs_ecc_error, - .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_fecs_ctxsw_mailbox, + .read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_mailbox_fecs_ctxsw, .fecs_host_clear_intr = gm20b_gr_falcon_fecs_host_clear_intr, .fecs_host_intr_status = gm20b_gr_falcon_fecs_host_intr_status, .fecs_base_addr = gm20b_gr_falcon_fecs_base_addr, @@ -665,8 +665,8 @@ static const struct gops_gr_falcon tu104_ops_gr_falcon = { .get_fecs_current_ctx_data = gm20b_gr_falcon_get_fecs_current_ctx_data, .init_ctx_state = gp10b_gr_falcon_init_ctx_state, .fecs_host_int_enable = gv11b_gr_falcon_fecs_host_int_enable, - .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_fecs_ctxsw_status0, - .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_fecs_ctxsw_status1, + .read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_status0_fecs_ctxsw, + .read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_status1_fecs_ctxsw, #ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT .load_ctxsw_ucode_header = gm20b_gr_falcon_load_ctxsw_ucode_header, .load_ctxsw_ucode_boot = gm20b_gr_falcon_load_ctxsw_ucode_boot, diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c index d78ab46fa..e071169af 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c @@ -278,8 +278,8 @@ static const struct gops_gr_ctxsw_prog vgpu_ga10b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, + .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, + .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr, diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c index b702dc328..3e23bfc57 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c @@ -252,8 +252,8 @@ static const struct gops_gr_ctxsw_prog vgpu_gv11b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, + .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, + .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/config.h b/drivers/gpu/nvgpu/include/nvgpu/gr/config.h index 28759b162..cba151d49 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/config.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/config.h @@ -186,7 +186,7 @@ u32 nvgpu_gr_config_get_gpc_ppc_count(struct nvgpu_gr_config *config, * * @return base address of array that stores number of TPCs in GPC. */ -u32 *nvgpu_gr_config_get_gpc_tpc_count_base(struct nvgpu_gr_config *config); +u32 *nvgpu_gr_config_get_base_count_gpc_tpc(struct nvgpu_gr_config *config); /** * @brief Get TPC count for given GPC. @@ -235,7 +235,7 @@ u32 nvgpu_gr_config_get_pes_tpc_count(struct nvgpu_gr_config *config, * * @return base address of array that stores mask of TPCs in GPC. */ -u32 *nvgpu_gr_config_get_gpc_tpc_mask_base(struct nvgpu_gr_config *config); +u32 *nvgpu_gr_config_get_base_mask_gpc_tpc(struct nvgpu_gr_config *config); /** * @brief Get TPC mask for given GPC. diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index 1d96199fd..5da765089 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c @@ -717,7 +717,7 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g, struct nvgpu_gr_config *gr_ err = copy_to_user((void __user *)(uintptr_t) args->mask_buf_addr, - nvgpu_gr_config_get_gpc_tpc_mask_base(gr_config), + nvgpu_gr_config_get_base_mask_gpc_tpc(gr_config), write_size); } diff --git a/drivers/gpu/nvgpu/os/linux/sysfs.c b/drivers/gpu/nvgpu/os/linux/sysfs.c index e7a22b6e1..8edf03e3a 100644 --- a/drivers/gpu/nvgpu/os/linux/sysfs.c +++ b/drivers/gpu/nvgpu/os/linux/sysfs.c @@ -926,7 +926,7 @@ static ssize_t tpc_fs_mask_store(struct device *dev, gr_golden_image = nvgpu_gr_get_golden_image_ptr(g); gr_falcon = nvgpu_gr_get_falcon_ptr(g); - if (nvgpu_gr_config_get_gpc_tpc_mask_base(gr_config) == NULL) + if (nvgpu_gr_config_get_base_mask_gpc_tpc(gr_config) == NULL) return -ENODEV; if (val && val != nvgpu_gr_config_get_gpc_tpc_mask(gr_config, 0) && diff --git a/libs/dgpu/libnvgpu-drv-dgpu_safe.export b/libs/dgpu/libnvgpu-drv-dgpu_safe.export index d05e00168..f520b2771 100644 --- a/libs/dgpu/libnvgpu-drv-dgpu_safe.export +++ b/libs/dgpu/libnvgpu-drv-dgpu_safe.export @@ -429,8 +429,8 @@ nvgpu_gr_config_get_gpc_tpc_count nvgpu_gr_config_get_pes_tpc_count nvgpu_gr_config_get_pes_tpc_mask nvgpu_gr_config_get_gpc_tpc_mask -nvgpu_gr_config_get_gpc_tpc_mask_base -nvgpu_gr_config_get_gpc_tpc_count_base +nvgpu_gr_config_get_base_mask_gpc_tpc +nvgpu_gr_config_get_base_count_gpc_tpc nvgpu_gr_config_get_sm_info nvgpu_gr_config_get_sm_info_global_tpc_index nvgpu_gr_config_get_sm_info_gpc_index diff --git a/libs/igpu/libnvgpu-drv-igpu_safe.export b/libs/igpu/libnvgpu-drv-igpu_safe.export index bfdeb26bd..34a260b6a 100644 --- a/libs/igpu/libnvgpu-drv-igpu_safe.export +++ b/libs/igpu/libnvgpu-drv-igpu_safe.export @@ -445,8 +445,8 @@ nvgpu_gr_config_get_gpc_tpc_count nvgpu_gr_config_get_pes_tpc_count nvgpu_gr_config_get_pes_tpc_mask nvgpu_gr_config_get_gpc_tpc_mask -nvgpu_gr_config_get_gpc_tpc_mask_base -nvgpu_gr_config_get_gpc_tpc_count_base +nvgpu_gr_config_get_base_mask_gpc_tpc +nvgpu_gr_config_get_base_count_gpc_tpc nvgpu_gr_config_get_sm_info nvgpu_gr_config_get_sm_info_global_tpc_index nvgpu_gr_config_get_sm_info_gpc_index diff --git a/userspace/units/gr/config/nvgpu-gr-config.c b/userspace/units/gr/config/nvgpu-gr-config.c index 2910f482f..51d740623 100644 --- a/userspace/units/gr/config/nvgpu-gr-config.c +++ b/userspace/units/gr/config/nvgpu-gr-config.c @@ -283,12 +283,12 @@ int test_gr_config_count(struct unit_module *m, /* * Check for valid memory */ - reg_base = nvgpu_gr_config_get_gpc_tpc_mask_base(unit_gr_config); + reg_base = nvgpu_gr_config_get_base_mask_gpc_tpc(unit_gr_config); if (reg_base == NULL) { unit_return_fail(m, "Invalid gpc_tpc_mask_base\n"); } - reg_base = nvgpu_gr_config_get_gpc_tpc_count_base(unit_gr_config); + reg_base = nvgpu_gr_config_get_base_count_gpc_tpc(unit_gr_config); if (reg_base == NULL) { unit_return_fail(m, "Invalid gpc_tpc_count_base\n"); } diff --git a/userspace/units/gr/config/nvgpu-gr-config.h b/userspace/units/gr/config/nvgpu-gr-config.h index 2b9376e58..fe06295a5 100644 --- a/userspace/units/gr/config/nvgpu-gr-config.h +++ b/userspace/units/gr/config/nvgpu-gr-config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -101,8 +101,8 @@ int test_gr_config_deinit(struct unit_module *m, struct gk20a *g, void *args); * nvgpu_gr_config_get_gpc_tpc_count, * nvgpu_gr_config_get_pes_tpc_count, * nvgpu_gr_config_get_pes_tpc_mask, - * nvgpu_gr_config_get_gpc_tpc_count_base, - * nvgpu_gr_config_get_gpc_tpc_mask_base + * nvgpu_gr_config_get_base_count_gpc_tpc, + * nvgpu_gr_config_get_base_mask_gpc_tpc * * Input: #test_gr_init_setup and #test_gr_config_init * must have been executed successfully. diff --git a/userspace/units/gr/intr/nvgpu-gr-intr.h b/userspace/units/gr/intr/nvgpu-gr-intr.h index f38054468..9e2bedf6a 100644 --- a/userspace/units/gr/intr/nvgpu-gr-intr.h +++ b/userspace/units/gr/intr/nvgpu-gr-intr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -48,7 +48,7 @@ struct unit_module; * nvgpu_gr_intr_handle_fecs_error, * gops_gr_falcon.dump_stats, * gm20b_gr_falcon_fecs_dump_stats, - * gm20b_gr_falcon_read_fecs_ctxsw_status1, + * gm20b_gr_falcon_read_status1_fecs_ctxsw, * gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size, * gm20b_gr_falcon_fecs_host_clear_intr, * nvgpu_gr_intr_remove_support @@ -172,11 +172,11 @@ int test_gr_intr_sw_exceptions(struct unit_module *m, * gops_gr_intr.get_ctxsw_checksum_mismatch_mailbox_val, * gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val, * gops_gr_falcon.read_fecs_ctxsw_mailbox, - * gm20b_gr_falcon_read_fecs_ctxsw_mailbox, + * gm20b_gr_falcon_read_mailbox_fecs_ctxsw, * gops_gr_falcon.dump_stats, * gm20b_gr_falcon_fecs_dump_stats, - * gm20b_gr_falcon_read_fecs_ctxsw_status1, - * gm20b_gr_falcon_read_fecs_ctxsw_status0, + * gm20b_gr_falcon_read_status1_fecs_ctxsw, + * gm20b_gr_falcon_read_status0_fecs_ctxsw, * gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size, * gm20b_gr_falcon_fecs_host_clear_intr, * gm20b_gr_falcon_fecs_host_intr_status, @@ -244,9 +244,9 @@ int test_gr_intr_fecs_exceptions(struct unit_module *m, * gops_gr_intr.record_sm_error_state, * gv11b_gr_intr_record_sm_error_state, * gops_gr_intr.get_sm_hww_warp_esr, - * gv11b_gr_intr_get_sm_hww_warp_esr, + * gv11b_gr_intr_get_warp_esr_sm_hww, * gops_gr_intr.get_sm_hww_warp_esr_pc, - * gv11b_gr_intr_get_sm_hww_warp_esr_pc, + * gv11b_gr_intr_get_warp_esr_sm_hww_pc, * gops_gr_intr.get_sm_hww_global_esr, * gv11b_gr_intr_get_sm_hww_global_esr, * gops_gr_intr.get_sm_no_lock_down_hww_global_esr_mask, diff --git a/userspace/units/gr/setup/nvgpu-gr-setup.h b/userspace/units/gr/setup/nvgpu-gr-setup.h index 0613b263c..1b8da685f 100644 --- a/userspace/units/gr/setup/nvgpu-gr-setup.h +++ b/userspace/units/gr/setup/nvgpu-gr-setup.h @@ -58,8 +58,8 @@ struct unit_module; * nvgpu_gr_ctx_get_global_ctx_va, * gops_gr_setup.alloc_obj_ctx, * nvgpu_gr_ctx_load_golden_ctx_image, - * gm20b_ctxsw_prog_set_priv_access_map_config_mode, - * gm20b_ctxsw_prog_set_priv_access_map_addr, + * gm20b_ctxsw_prog_set_config_mode_priv_access_map, + * gm20b_ctxsw_prog_set_addr_priv_access_map, * gm20b_ctxsw_prog_set_patch_addr, * gm20b_ctxsw_prog_disable_verif_features, * gv11b_gr_init_commit_global_attrib_cb,