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gpu: nvgpu: add base_shift and alloc_size ramin HALs

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Added the following HALs
- ramin.base_shift
- ramin.alloc_base

Use above HALs in mm, instead of using hw definitions.

Defined nvgpu_inst_block_ptr to
- get inst_block address,
- shift if by base_shift
- assert upper 32 bits are 0
- return lower 32 bits

Added missing #include for <nvgpu/mm.h>

Jira NVGPU-3015

Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-03-20 16:55:08 -07:00
committed by mobile promotions
parent 80b91ef2a5
commit 4ef4939797
35 changed files with 94 additions and 63 deletions
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7
drivers/gpu/nvgpu/common/perf/perf_gv11b.c
View File

@@ -74,7 +74,7 @@ void gv11b_perf_enable_membuf(struct gk20a *g, u32 size,
{
u32 addr_lo;
u32 addr_hi;
u64 inst_block_addr;
u32 inst_block_ptr;
addr_lo = u64_lo32(buf_addr);
addr_hi = u64_hi32(buf_addr);
@@ -84,11 +84,10 @@ void gv11b_perf_enable_membuf(struct gk20a *g, u32 size,
perf_pmasys_outbaseupper_ptr_f(addr_hi));
nvgpu_writel(g, perf_pmasys_outsize_r(), size);
inst_block_addr = nvgpu_inst_block_addr(g, inst_block) >> 12;
inst_block_ptr = nvgpu_inst_block_ptr(g, inst_block);
nvgpu_assert(inst_block_addr <= U64(U32_MAX));
nvgpu_writel(g, perf_pmasys_mem_block_r(),
perf_pmasys_mem_block_base_f(U32(inst_block_addr)) |
perf_pmasys_mem_block_base_f(inst_block_ptr) |
perf_pmasys_mem_block_valid_true_f() |
nvgpu_aperture_mask(g, inst_block,
perf_pmasys_mem_block_target_sys_ncoh_f(),