nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 09:12:24 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: add base_shift and alloc_size ramin HALs

Browse Source 
Added the following HALs
- ramin.base_shift
- ramin.alloc_base

Use above HALs in mm, instead of using hw definitions.

Defined nvgpu_inst_block_ptr to
- get inst_block address,
- shift if by base_shift
- assert upper 32 bits are 0
- return lower 32 bits

Added missing #include for <nvgpu/mm.h>

Jira NVGPU-3015

Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-03-20 16:55:08 -07:00
committed by mobile promotions
parent 80b91ef2a5
commit 4ef4939797
35 changed files with 94 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
userspace/units/mm/gmmu/page_table/page_table.c
View File

@@ -43,6 +43,7 @@
#include <hal/fb/fb_gp10b.h>
#include <hal/fb/fb_gm20b.h>
#include <hal/fifo/ramin_gk20a.h>
#include <hal/fifo/ramin_gp10b.h>
#define TEST_PA_ADDRESS 0xEFAD80000000
@@ -305,6 +306,7 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
g->ops.fb.compression_page_size = gp10b_fb_compression_page_size;
g->ops.fb.tlb_invalidate = gm20b_fb_tlb_invalidate;
g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
if (g->ops.mm.is_bar1_supported(g)) {
unit_return_fail(m, "BAR1 is not supported on Volta+\n");