From 4f45ec7d5f5646177bc3e1c322d0caad07107600 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Tue, 26 Nov 2019 10:57:32 -0800 Subject: [PATCH] gpu: nvgpu: unit: mm: flush_gk20a_fusa unit test This unit test covers most of the nvgpu.hal.mm.cache.flush_gk20a_fusa module lines and almost all branches. Jira NVGPU-2218 Change-Id: I1c090a301a7d1fddb675248287e7d4c7b9da0538 Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/2248084 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- Makefile.umbrella.tmk | 1 + drivers/gpu/nvgpu/libnvgpu-drv_safe.export | 2 + userspace/Makefile.sources | 3 +- userspace/SWUTS.h | 1 + userspace/SWUTS.sources | 1 + userspace/required_tests.json | 120 +++++ .../mm/hal/cache/flush_gk20a_fusa/Makefile | 26 + .../flush_gk20a_fusa/Makefile.interface.tmk | 35 ++ .../hal/cache/flush_gk20a_fusa/Makefile.tmk | 35 ++ .../cache/flush_gk20a_fusa/flush-gk20a-fusa.c | 457 ++++++++++++++++++ .../cache/flush_gk20a_fusa/flush-gk20a-fusa.h | 150 ++++++ 11 files changed, 830 insertions(+), 1 deletion(-) create mode 100644 userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile create mode 100644 userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.interface.tmk create mode 100644 userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.tmk create mode 100644 userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.c create mode 100644 userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.h diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk index 405e22fb3..c8994ba2a 100644 --- a/Makefile.umbrella.tmk +++ b/Makefile.umbrella.tmk @@ -64,6 +64,7 @@ NV_REPOSITORY_COMPONENTS += userspace/units/mm/as NV_REPOSITORY_COMPONENTS += userspace/units/mm/dma NV_REPOSITORY_COMPONENTS += userspace/units/mm/gmmu/pd_cache NV_REPOSITORY_COMPONENTS += userspace/units/mm/gmmu/page_table +NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/cache/flush_gk20a_fusa NV_REPOSITORY_COMPONENTS += userspace/units/mm/mm NV_REPOSITORY_COMPONENTS += userspace/units/mm/page_table_faults NV_REPOSITORY_COMPONENTS += userspace/units/mm/vm diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export index 4aeed7620..ad0b26b14 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export @@ -24,6 +24,8 @@ gk20a_fifo_intr_handle_chsw_error gk20a_fifo_intr_handle_runlist_event gk20a_fifo_pbdma_isr gk20a_mm_fb_flush +gk20a_mm_l2_flush +gk20a_mm_l2_invalidate gk20a_ptimer_isr gk20a_ramin_alloc_size gk20a_ramin_base_shift diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index dc6d26189..04729bd3a 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -71,6 +71,7 @@ UNITS := \ $(UNIT_SRC)/mm/dma \ $(UNIT_SRC)/mm/gmmu/pd_cache \ $(UNIT_SRC)/mm/gmmu/page_table \ + $(UNIT_SRC)/mm/hal/cache/flush_gk20a_fusa \ $(UNIT_SRC)/mm/mm \ $(UNIT_SRC)/mm/page_table_faults \ $(UNIT_SRC)/mm/nvgpu_mem \ @@ -104,7 +105,7 @@ UNITS := \ $(UNIT_SRC)/ltc \ $(UNIT_SRC)/enabled \ $(UNIT_SRC)/falcon \ - $(UNIT_SRC)/falcon/falcon_tests \ + $(UNIT_SRC)/falcon/falcon_tests \ $(UNIT_SRC)/fuse \ $(UNIT_SRC)/pmu \ $(UNIT_SRC)/top \ diff --git a/userspace/SWUTS.h b/userspace/SWUTS.h index 05bc19c2c..63d39fe85 100644 --- a/userspace/SWUTS.h +++ b/userspace/SWUTS.h @@ -67,6 +67,7 @@ * - @ref SWUTS-mm-as * - @ref SWUTS-mm-dma * - @ref SWUTS-mm-gmmu-page_table + * - @ref SWUTS-mm-hal-cache-flush-gk20a-fusa * - @ref SWUTS-mm-nvgpu-mem * - @ref SWUTS-mm-nvgpu-sgt * - @ref SWUTS-mm-page_table_faults diff --git a/userspace/SWUTS.sources b/userspace/SWUTS.sources index 3437b9d95..15523bed5 100644 --- a/userspace/SWUTS.sources +++ b/userspace/SWUTS.sources @@ -42,6 +42,7 @@ INPUT += ../../../userspace/units/mm/allocators/buddy_allocator/buddy_allocator. INPUT += ../../../userspace/units/mm/as/as.h INPUT += ../../../userspace/units/mm/dma/dma.h INPUT += ../../../userspace/units/mm/gmmu/page_table/page_table.h +INPUT += ../../../userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.h INPUT += ../../../userspace/units/mm/nvgpu_mem/nvgpu_mem.h INPUT += ../../../userspace/units/mm/nvgpu_sgt/nvgpu_sgt.h INPUT += ../../../userspace/units/mm/page_table_faults/page_table_faults.h diff --git a/userspace/required_tests.json b/userspace/required_tests.json index 9f5739bf4..a5d049139 100644 --- a/userspace/required_tests.json +++ b/userspace/required_tests.json @@ -701,6 +701,126 @@ "unit": "fbp", "test_level": 0 }, + { + "test": "test_env_clean", + "case": "env_clean", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_env_init", + "case": "env_init", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_fb_flush", + "case": "mm_fb_flush_s0", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_fb_flush", + "case": "mm_fb_flush_s1", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_fb_flush", + "case": "mm_fb_flush_s2", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_fb_flush", + "case": "mm_fb_flush_s3", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_fb_flush", + "case": "mm_fb_flush_s4", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_fb_flush", + "case": "mm_fb_flush_s5", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_fb_flush", + "case": "mm_fb_flush_s6", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_flush", + "case": "mm_l2_flush_s0", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_flush", + "case": "mm_l2_flush_s1", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_flush", + "case": "mm_l2_flush_s2", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_flush", + "case": "mm_l2_flush_s3", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_flush", + "case": "mm_l2_flush_s4", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_flush", + "case": "mm_l2_flush_s5", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_invalidate", + "case": "mm_l2_invalidate_s0", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_invalidate", + "case": "mm_l2_invalidate_s1", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_invalidate", + "case": "mm_l2_invalidate_s2", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_invalidate", + "case": "mm_l2_invalidate_s3", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_mm_l2_invalidate", + "case": "mm_l2_invalidate_s4", + "unit": "flush_gk20a_fusa", + "test_level": 0 + }, { "test": "test_fuse_gm20b_basic_fuses", "case": "fuse_gm20b_basic_fuses", diff --git a/userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile b/userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile new file mode 100644 index 000000000..e371884e5 --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile @@ -0,0 +1,26 @@ +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = flush-gk20a-fusa.o +MODULE = flush-gk20a-fusa + +include ../../../../Makefile.units diff --git a/userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.interface.tmk b/userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.interface.tmk new file mode 100644 index 000000000..0b2c18934 --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=flush-gk20a-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.tmk b/userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.tmk new file mode 100644 index 000000000..5e016f601 --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=flush-gk20a-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.c b/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.c new file mode 100644 index 000000000..bd7e03fba --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.c @@ -0,0 +1,457 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include "os/posix/os_posix.h" + +#include "hal/fb/fb_gv11b.h" +#include "hal/fb/intr/fb_intr_gv11b.h" +#include "hal/fifo/ramin_gk20a.h" +#include "hal/fifo/ramin_gp10b.h" +#include "hal/mm/cache/flush_gk20a.h" +#include "hal/mm/gmmu/gmmu_gp10b.h" +#include "hal/mm/mm_gp10b.h" +#include "hal/mm/mm_gv11b.h" +#include "hal/mm/mmu_fault/mmu_fault_gv11b.h" + +#include "hal/mm/cache/flush_gk20a.h" + +#include + +#include +#include + +#include "flush-gk20a-fusa.h" + +/* + * Write callback (for all nvgpu_writel calls). + */ +#define WR_FLUSH_0 0 +#define WR_FLUSH_1 1 +#define WR_FLUSH_2 2 +#define WR_FLUSH_3 3 +#define WR_FLUSH_ACTUAL 0 +#define WR_FLUSH_TEST_FB_FLUSH_ADDR 1 +#define WR_FLUSH_TEST_L2_FLUSH_DIRTY_ADDR 2 +#define WR_FLUSH_TEST_L2_SYSTEM_INVALIDATE 3 + +static u32 write_specific_value; +static u32 write_specific_addr; + +static void writel_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + if (((write_specific_addr == WR_FLUSH_TEST_FB_FLUSH_ADDR) && + (access->addr == flush_fb_flush_r())) || + ((write_specific_addr == WR_FLUSH_TEST_L2_FLUSH_DIRTY_ADDR) && + (access->addr == flush_l2_flush_dirty_r())) || + ((write_specific_addr == WR_FLUSH_TEST_L2_SYSTEM_INVALIDATE) && + (access->addr == flush_l2_system_invalidate_r()))) { + nvgpu_posix_io_writel_reg_space(g, access->addr, + write_specific_value); + } else { + nvgpu_posix_io_writel_reg_space(g, access->addr, access->value); + } +} + +/* + * Read callback, similar to the write callback above. + */ +static void readl_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + access->value = nvgpu_posix_io_readl_reg_space(g, access->addr); +} + +/* + * Define all the callbacks to be used during the test. Typically all + * write operations use the same callback, likewise for all read operations. + */ +static struct nvgpu_posix_io_callbacks mmu_faults_callbacks = { + /* Write APIs all can use the same accessor. */ + .writel = writel_access_reg_fn, + .writel_check = writel_access_reg_fn, + .bar1_writel = writel_access_reg_fn, + .usermode_writel = writel_access_reg_fn, + + /* Likewise for the read APIs. */ + .__readl = readl_access_reg_fn, + .readl = readl_access_reg_fn, + .bar1_readl = readl_access_reg_fn, +}; + +static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU) +{ + if (is_iGPU) { + nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true); + } else { + nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false); + } +} + +static int init_mm(struct unit_module *m, struct gk20a *g) +{ + u64 low_hole, aperture_size; + struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g); + struct mm_gk20a *mm = &g->mm; + + p->mm_is_iommuable = true; + + /* Minimum HALs for page_table */ + g->ops.mm.gmmu.get_default_big_page_size = + gp10b_mm_get_default_big_page_size; + g->ops.mm.init_inst_block = gv11b_mm_init_inst_block; + g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels; + g->ops.ramin.init_pdb = gp10b_ramin_init_pdb; + g->ops.ramin.alloc_size = gk20a_ramin_alloc_size; + g->ops.mm.setup_hw = nvgpu_mm_setup_hw; + g->ops.fb.init_hw = gv11b_fb_init_hw; + g->ops.fb.intr.enable = gv11b_fb_intr_enable; + g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush; + g->ops.mm.mmu_fault.info_mem_destroy = + gv11b_mm_mmu_fault_info_mem_destroy; + + nvgpu_posix_register_io(g, &mmu_faults_callbacks); + nvgpu_posix_io_init_reg_space(g); + + /* Register space: FB_MMU */ + if (nvgpu_posix_io_add_reg_space(g, flush_fb_flush_r(), 0x800) != 0) { + unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n"); + } + + /* + * Initialize VM space for system memory to be used throughout this + * unit module. + * Values below are similar to those used in nvgpu_init_system_vm() + */ + low_hole = SZ_4K * 16UL; + aperture_size = GK20A_PMU_VA_SIZE; + mm->pmu.aperture_size = GK20A_PMU_VA_SIZE; + + mm->pmu.vm = nvgpu_vm_init(g, + g->ops.mm.gmmu.get_default_big_page_size(), + low_hole, + aperture_size - low_hole, + aperture_size, + true, + false, + false, + "system"); + if (mm->pmu.vm == NULL) { + unit_return_fail(m, "'system' nvgpu_vm_init failed\n"); + } + + /* + * This initialization will make sure that correct aperture mask + * is returned */ + g->mm.mmu_wr_mem.aperture = APERTURE_SYSMEM; + g->mm.mmu_rd_mem.aperture = APERTURE_SYSMEM; + + return UNIT_SUCCESS; +} + +int test_env_init(struct unit_module *m, struct gk20a *g, void *args) +{ + g->log_mask = 0; + + init_platform(m, g, true); + + if (init_mm(m, g) != 0) { + unit_return_fail(m, "nvgpu_init_mm_support failed\n"); + } + + write_specific_value = 0; + write_specific_addr = 0; + + return UNIT_SUCCESS; +} + +#define F_GK20A_FB_FLUSH_DEFAULT_INPUT 0 +#define F_GK20A_FB_FLUSH_GET_RETRIES 1 +#define F_GK20A_FB_FLUSH_PENDING_TRUE 2 +#define F_GK20A_FB_FLUSH_OUTSTANDING_TRUE 3 +#define F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE 4 +#define F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO 5 +#define F_GK20A_FB_FLUSH_NVGPU_POWERED_OFF 6 + +const char *m_gk20a_mm_fb_flush_str[] = { + "default_input", + "get_flush_retries", + "fb_flush_pending_true", + "fb_flush_outstanding_true", + "fb_flush_outstanding_pending_true", + "nvgpu_powered_off", +}; + +static u32 stub_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op) +{ + return 100U; +} + +static void stub_fb_dump_vpr_info(struct gk20a *g) +{ +} + +static void stub_fb_dump_wpr_info(struct gk20a *g) +{ +} + +int test_gk20a_mm_fb_flush(struct unit_module *m, struct gk20a *g, void *args) +{ + int err; + int ret = UNIT_FAIL; + u64 branch = (u64)args; + + nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON); + write_specific_addr = WR_FLUSH_TEST_FB_FLUSH_ADDR; + + switch (branch) { + case F_GK20A_FB_FLUSH_PENDING_TRUE: + write_specific_value = WR_FLUSH_1; + break; + case F_GK20A_FB_FLUSH_OUTSTANDING_TRUE: + write_specific_value = WR_FLUSH_2; + break; + case F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE: + write_specific_value = WR_FLUSH_3; + break; + case F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO: + write_specific_value = WR_FLUSH_1; + break; + default: + write_specific_value = WR_FLUSH_0; + break; + } + + g->ops.mm.get_flush_retries = branch == F_GK20A_FB_FLUSH_GET_RETRIES ? + stub_mm_get_flush_retries : NULL; + + g->ops.fb.dump_vpr_info = branch == F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO ? + stub_fb_dump_vpr_info : NULL; + + g->ops.fb.dump_wpr_info = branch == F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO ? + stub_fb_dump_wpr_info : NULL; + + if (branch == F_GK20A_FB_FLUSH_NVGPU_POWERED_OFF) { + nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF); + } + + err = gk20a_mm_fb_flush(g); + + if ((branch == F_GK20A_FB_FLUSH_PENDING_TRUE) || + (branch == F_GK20A_FB_FLUSH_OUTSTANDING_TRUE) || + (branch == F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE) || + (branch == F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO)) { + unit_assert(err != 0, goto done); + } else { + unit_assert(err == 0, goto done); + } + + ret = UNIT_SUCCESS; +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: failed at %s\n", __func__, + m_gk20a_mm_fb_flush_str[branch]); + } + write_specific_addr = WR_FLUSH_ACTUAL; + return ret; +} + +#define F_GK20A_L2_FLUSH_DEFAULT_INPUT 0 +#define F_GK20A_L2_FLUSH_GET_RETRIES 1 +#define F_GK20A_L2_FLUSH_PENDING_TRUE 2 +#define F_GK20A_L2_FLUSH_OUTSTANDING_TRUE 3 +#define F_GK20A_L2_FLUSH_INVALIDATE 4 +#define F_GK20A_L2_FLUSH_NVGPU_POWERED_OFF 5 + +const char *m_gk20a_mm_l2_flush_str[] = { + "default_input", + "get_flush_retries", + "l2_flush_pending_true", + "l2_flush_outstanding_true", + "l2_flush_invalidate", + "nvgpu_powered_off", +}; + +int test_gk20a_mm_l2_flush(struct unit_module *m, struct gk20a *g, void *args) +{ + int err; + int ret = UNIT_FAIL; + u64 branch = (u64)args; + bool invalidate; + + nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON); + write_specific_addr = WR_FLUSH_TEST_L2_FLUSH_DIRTY_ADDR; + + switch (branch) { + case F_GK20A_L2_FLUSH_PENDING_TRUE: + write_specific_value = WR_FLUSH_1; + break; + case F_GK20A_L2_FLUSH_OUTSTANDING_TRUE: + write_specific_value = WR_FLUSH_2; + break; + default: + write_specific_value = WR_FLUSH_0; + break; + } + + g->ops.mm.get_flush_retries = (branch == F_GK20A_L2_FLUSH_GET_RETRIES) ? + stub_mm_get_flush_retries : NULL; + + invalidate = (branch == F_GK20A_L2_FLUSH_INVALIDATE) ? true : false; + + if (branch == F_GK20A_L2_FLUSH_NVGPU_POWERED_OFF) { + nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF); + } + + err = gk20a_mm_l2_flush(g, invalidate); + + if ((branch == F_GK20A_L2_FLUSH_PENDING_TRUE) || + (branch == F_GK20A_L2_FLUSH_OUTSTANDING_TRUE) || + (branch == F_GK20A_L2_FLUSH_NVGPU_POWERED_OFF)) { + unit_assert(err != 0, goto done); + } else { + unit_assert(err == 0, goto done); + } + + ret = UNIT_SUCCESS; +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: failed at %s\n", __func__, + m_gk20a_mm_l2_flush_str[branch]); + } + write_specific_addr = WR_FLUSH_ACTUAL; + return ret; +} + +#define F_GK20A_L2_INVALIDATE_DEFAULT_INPUT 0 +#define F_GK20A_L2_INVALIDATE_PENDING_TRUE 1 +#define F_GK20A_L2_INVALIDATE_OUTSTANDING_TRUE 2 +#define F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL 3 +#define F_GK20A_L2_INVALIDATE_NVGPU_POWERED_OFF 4 + + +const char *m_gk20a_mm_l2_invalidate_str[] = { + "invalidate_default_input", + "invalidate_l2_pending_true", + "invalidate_l2_outstanding_true", + "invalidate_get_flush_retries_null", +}; + +static u32 global_count = 100; +static u32 count; + +static u32 stub_mm_get_flush_retries_count(struct gk20a *g, + enum nvgpu_flush_op op) +{ + count = global_count++; + return 100U; +} + +int test_gk20a_mm_l2_invalidate(struct unit_module *m, struct gk20a *g, + void *args) +{ + int ret = UNIT_FAIL; + u64 branch = (u64)args; + + nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON); + write_specific_addr = WR_FLUSH_TEST_L2_SYSTEM_INVALIDATE; + + switch (branch) { + case F_GK20A_L2_INVALIDATE_PENDING_TRUE: + write_specific_value = WR_FLUSH_1; + break; + case F_GK20A_L2_INVALIDATE_OUTSTANDING_TRUE: + write_specific_value = WR_FLUSH_2; + break; + default: + write_specific_value = WR_FLUSH_0; + break; + } + + g->ops.mm.get_flush_retries = + (branch == F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL) ? + NULL : stub_mm_get_flush_retries_count; + + if (branch == F_GK20A_L2_INVALIDATE_NVGPU_POWERED_OFF) { + nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF); + } + + gk20a_mm_l2_invalidate(g); + + if (branch != F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL) { + unit_assert(count == (global_count - 1U), goto done); + } + + ret = UNIT_SUCCESS; +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: failed at %s\n", __func__, + m_gk20a_mm_l2_invalidate_str[branch]); + } + write_specific_addr = WR_FLUSH_ACTUAL; + return ret; +} + +int test_env_clean(struct unit_module *m, struct gk20a *g, void *args) +{ + g->log_mask = 0; + + nvgpu_vm_put(g->mm.pmu.vm); + + return UNIT_SUCCESS; +} + +struct unit_module_test mm_flush_gk20a_fusa_tests[] = { + UNIT_TEST(env_init, test_env_init, NULL, 0), + UNIT_TEST(mm_fb_flush_s0, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_DEFAULT_INPUT, 0), + UNIT_TEST(mm_fb_flush_s1, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_GET_RETRIES, 0), + UNIT_TEST(mm_fb_flush_s2, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_PENDING_TRUE, 0), + UNIT_TEST(mm_fb_flush_s3, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_OUTSTANDING_TRUE, 0), + UNIT_TEST(mm_fb_flush_s4, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE, 0), + UNIT_TEST(mm_fb_flush_s5, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO, 0), + UNIT_TEST(mm_fb_flush_s6, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_NVGPU_POWERED_OFF, 0), + UNIT_TEST(mm_l2_flush_s0, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_DEFAULT_INPUT, 0), + UNIT_TEST(mm_l2_flush_s1, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_GET_RETRIES, 0), + UNIT_TEST(mm_l2_flush_s2, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_PENDING_TRUE, 0), + UNIT_TEST(mm_l2_flush_s3, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_OUTSTANDING_TRUE, 0), + UNIT_TEST(mm_l2_flush_s4, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_INVALIDATE, 0), + UNIT_TEST(mm_l2_flush_s5, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_NVGPU_POWERED_OFF, 0), + UNIT_TEST(mm_l2_invalidate_s0, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_DEFAULT_INPUT, 0), + UNIT_TEST(mm_l2_invalidate_s1, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_PENDING_TRUE, 0), + UNIT_TEST(mm_l2_invalidate_s2, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_OUTSTANDING_TRUE, 0), + UNIT_TEST(mm_l2_invalidate_s3, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL, 0), + UNIT_TEST(mm_l2_invalidate_s4, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_NVGPU_POWERED_OFF, 0), + UNIT_TEST(env_clean, test_env_clean, NULL, 0), +}; + +UNIT_MODULE(flush_gk20a_fusa, mm_flush_gk20a_fusa_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.h b/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.h new file mode 100644 index 000000000..86cb57a81 --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef UNIT_MM_HAL_CACHE_FLUSH_GK20A_FUSA_H +#define UNIT_MM_HAL_CACHE_FLUSH_GK20A_FUSA_H + +struct gk20a; +struct unit_module; + +/** @addtogroup SWUTS-mm-hal-cache-flush-gk20a-fusa + * @{ + * + * Software Unit Test Specification for mm.hal.cache.flush_gk20a_fusa + */ + +/** + * Test specification for: test_env_init + * + * Description: Initialize environment for MM tests + * + * Test Type: Feature based + * + * Targets: None + * + * Input: None + * + * Steps: + * - Init HALs and initialize VMs similar to nvgpu_init_system_vm(). + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_env_init(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_gk20a_mm_fb_flush + * + * Description: Test FB flush + * + * Test Type: Feature based + * + * Targets: gk20a_mm_fb_flush + * + * Input: test_env_init, args (value can be F_GK20A_FB_FLUSH_DEFAULT_INPUT, + * F_GK20A_FB_FLUSH_GET_RETRIES, F_GK20A_FB_FLUSH_PENDING_TRUE, + * F_GK20A_FB_FLUSH_OUTSTANDING_TRUE, + * F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE, + * F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO or + * F_GK20A_FB_FLUSH_NVGPU_POWERED_OFF) + * + * Steps: + * - Invoke FB flush command + * - Test FB flush with various scenarios as below: + * - flush outstanding, flush pending, GPU powered off + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gk20a_mm_fb_flush(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_gk20a_mm_l2_flush + * + * Description: Test L2 flush + * + * Test Type: Feature based + * + * Targets: gk20a_mm_l2_flush, gk20a_mm_l2_invalidate_locked + * + * Input: test_env_init, args (value can be F_GK20A_L2_FLUSH_DEFAULT_INPUT, + * F_GK20A_L2_FLUSH_GET_RETRIES, F_GK20A_L2_FLUSH_PENDING_TRUE, + * F_GK20A_L2_FLUSH_OUTSTANDING_TRUE, F_GK20A_L2_FLUSH_INVALIDATE or + * F_GK20A_L2_FLUSH_NVGPU_POWERED_OFF) + * + * Steps: + * - Invoke L2 flush command + * - Test L2 flush with various scenarios as below: + * - flush dirty outstanding, flush dirty pending, GPU powered off, + * flush with invalidate + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gk20a_mm_l2_flush(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_gk20a_mm_l2_invalidate + * + * Description: Test L2 invalidate + * + * Test Type: Feature based + * + * Targets: gk20a_mm_l2_invalidate, gk20a_mm_l2_invalidate_locked + * + * Input: test_env_init, args (value can be F_GK20A_L2_INVALIDATE_DEFAULT_INPUT, + * F_GK20A_L2_INVALIDATE_PENDING_TRUE, + * F_GK20A_L2_INVALIDATE_OUTSTANDING_TRUE, + * F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL or + * F_GK20A_L2_INVALIDATE_NVGPU_POWERED_OFF) + * + * Steps: + * - Invoke L2 invalidate + * - Test when invalidate is outstanding and/or pending + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gk20a_mm_l2_invalidate(struct unit_module *m, struct gk20a *g, + void *args); + +/** + * Test specification for: test_env_clean + * + * Description: Cleanup test environment + * + * Test Type: Feature based + * + * Targets: None + * + * Input: test_env_init + * + * Steps: + * - Destroy memory and VMs initialized for the test. + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_env_clean(struct unit_module *m, struct gk20a *g, void *args); + +/** @} */ +#endif /* UNIT_MM_HAL_CACHE_FLUSH_GK20A_FUSA_H */