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gpu: nvgpu: Implement clk_good and pll_lock check

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Add clk_good and pll_lock check as a part of fmon polling.
This will poll for any clock related faults at FTTI interval.
Add new function to poll for vbios init completion.

NVGPU-4967
Bug 2849506
Bug 200564937

Change-Id: I5bc885329981e07376824e148edabe9be4120e1c
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2305782
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2020-03-24 22:19:53 +05:30
committed by Alex Waterman
parent b8a3e54dda
commit 4f5bd9e633
9 changed files with 116 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/include/nvgpu/bios.h
View File

@@ -1505,4 +1505,5 @@ u32 nvgpu_bios_get_vbios_version(struct gk20a *g);
u8 nvgpu_bios_get_vbios_oem_version(struct gk20a *g);
struct bit_token *nvgpu_bios_get_bit_token(struct gk20a *g,
u8 token_id);
bool nvgpu_bios_wait_for_init_done(struct gk20a *g);
#endif

5
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -373,6 +373,10 @@ struct gpu_ops {
struct clk_domains_mon_status_params *clk_mon_status,
u32 domain_mask);
u32 (*clk_mon_init_domains)(struct gk20a *g);
#ifdef CONFIG_NVGPU_DGPU
bool (*clk_mon_check_clk_good)(struct gk20a *g);
bool (*clk_mon_check_pll_lock)(struct gk20a *g);
#endif
} clk;
#ifdef CONFIG_NVGPU_CLK_ARB
struct {
@@ -468,6 +472,7 @@ struct gpu_ops {
void (*bios_sw_deinit)(struct gk20a *g,
struct nvgpu_bios *bios);
u32 (*get_aon_secure_scratch_reg)(struct gk20a *g, u32 i);
bool (*wait_for_bios_init_done)(struct gk20a *g);
} bios;
#if defined(CONFIG_NVGPU_CYCLESTATS)

19
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -210,4 +210,21 @@
#define trim_fmon_master_status_r() (0x00137a00U)
#define trim_fmon_master_status_fault_out_v(r) (((r) >> 0U) & 0x1U)
#define trim_fmon_master_status_fault_out_true_v() (0x00000001U)
#define trim_xtal4x_cfg5_r() (0x001370c0U)
#define trim_xtal4x_cfg5_curr_state_v(r) (((r) >> 16U) & 0xfU)
#define trim_xtal4x_cfg5_curr_state_good_v() (0x00000006U)
#define trim_xtal4x_cfg_r() (0x001370a0U)
#define trim_xtal4x_cfg_pll_lock_v(r) (((r) >> 17U) & 0x1U)
#define trim_xtal4x_cfg_pll_lock_true_v() (0x00000001U)
#define trim_mem_pll_status_r() (0x00137390U)
#define trim_mem_pll_status_dram_curr_state_v(r) (((r) >> 1U) & 0x1U)
#define trim_mem_pll_status_dram_curr_state_good_v() (0x00000001U)
#define trim_mem_pll_status_refm_curr_state_v(r) (((r) >> 17U) & 0x1U)
#define trim_mem_pll_status_refm_curr_state_good_v() (0x00000001U)
#define trim_sppll0_cfg_r() (0x0000e800U)
#define trim_sppll0_cfg_curr_state_v(r) (((r) >> 17U) & 0x1U)
#define trim_sppll0_cfg_curr_state_good_v() (0x00000001U)
#define trim_sppll1_cfg_r() (0x0000e820U)
#define trim_sppll1_cfg_curr_state_v(r) (((r) >> 17U) & 0x1U)
#define trim_sppll1_cfg_curr_state_good_v() (0x00000001U)
#endif