From 4faeea63aa55a1ecab973a60a0b70876d3e2d67d Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 11 Apr 2019 12:01:03 -0700 Subject: [PATCH] gpu: nvgpu: create class unit Created class unit under hal and moved all valid class check related functionality to this unit. Moved all class defs from gr to a new header include/nvgpu/class.h. Moved following hals from gr to newly created class unit: bool (*is_valid_class)(struct gk20a *g, u32 class_num); --> bool (*is_valid)(u32 class_num); bool (*is_valid_gfx_class)(struct gk20a *g, u32 class_num); --> bool (*is_valid_gfx)(u32 class_num); bool (*is_valid_compute_class)(struct gk20a *g, u32 class_num); --> bool (*is_valid_compute)(u32 class_num); JIRA NVGPU-3109 Change-Id: I01123e9b984613d4bddb2d8cf23d63410e212408 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2095542 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 4 + drivers/gpu/nvgpu/Makefile.sources | 4 + drivers/gpu/nvgpu/common/gr/gr_setup.c | 2 +- drivers/gpu/nvgpu/common/gr/obj_ctx.c | 10 +- .../nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c | 10 +- drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c | 12 +-- .../nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c | 10 +- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 39 +------- drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 9 +- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 11 ++- drivers/gpu/nvgpu/gp106/gr_gp106.c | 30 +----- drivers/gpu/nvgpu/gp106/gr_gp106.h | 4 - drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 45 +-------- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 9 -- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 11 ++- drivers/gpu/nvgpu/gv100/hal_gv100.c | 11 ++- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 67 +------------- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 9 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 11 ++- drivers/gpu/nvgpu/hal/class/class_gm20b.c | 63 +++++++++++++ drivers/gpu/nvgpu/hal/class/class_gm20b.h | 32 +++++++ drivers/gpu/nvgpu/hal/class/class_gp10b.c | 70 ++++++++++++++ drivers/gpu/nvgpu/hal/class/class_gp10b.h | 32 +++++++ drivers/gpu/nvgpu/hal/class/class_gv11b.c | 91 +++++++++++++++++++ drivers/gpu/nvgpu/hal/class/class_gv11b.h | 32 +++++++ drivers/gpu/nvgpu/hal/class/class_tu104.c | 69 ++++++++++++++ drivers/gpu/nvgpu/hal/class/class_tu104.h | 32 +++++++ drivers/gpu/nvgpu/include/nvgpu/class.h | 55 +++++++++++ drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 18 ++-- drivers/gpu/nvgpu/tu104/gr_tu104.c | 43 +-------- drivers/gpu/nvgpu/tu104/gr_tu104.h | 9 +- drivers/gpu/nvgpu/tu104/hal_tu104.c | 11 ++- 32 files changed, 565 insertions(+), 300 deletions(-) create mode 100644 drivers/gpu/nvgpu/hal/class/class_gm20b.c create mode 100644 drivers/gpu/nvgpu/hal/class/class_gm20b.h create mode 100644 drivers/gpu/nvgpu/hal/class/class_gp10b.c create mode 100644 drivers/gpu/nvgpu/hal/class/class_gp10b.h create mode 100644 drivers/gpu/nvgpu/hal/class/class_gv11b.c create mode 100644 drivers/gpu/nvgpu/hal/class/class_gv11b.h create mode 100644 drivers/gpu/nvgpu/hal/class/class_tu104.c create mode 100644 drivers/gpu/nvgpu/hal/class/class_tu104.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/class.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 83873da96..0673e81b6 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -165,6 +165,10 @@ nvgpu-y += \ hal/bus/bus_gp10b.o \ hal/bus/bus_gv100.o \ hal/bus/bus_tu104.o \ + hal/class/class_gm20b.o \ + hal/class/class_gp10b.o \ + hal/class/class_gv11b.o \ + hal/class/class_tu104.o \ hal/gr/ecc/ecc_gp10b.o \ hal/gr/ecc/ecc_gv11b.o \ hal/gr/ecc/ecc_tu104.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 4611f1966..e37ad6a32 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -289,6 +289,10 @@ srcs += common/sim.c \ hal/bus/bus_gp10b.c \ hal/bus/bus_gv100.c \ hal/bus/bus_tu104.c \ + hal/class/class_gm20b.c \ + hal/class/class_gp10b.c \ + hal/class/class_gv11b.c \ + hal/class/class_tu104.c \ hal/gr/ecc/ecc_gp10b.c \ hal/gr/ecc/ecc_gv11b.c \ hal/gr/ecc/ecc_tu104.c \ diff --git a/drivers/gpu/nvgpu/common/gr/gr_setup.c b/drivers/gpu/nvgpu/common/gr/gr_setup.c index c847075f6..485c1f68a 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_setup.c +++ b/drivers/gpu/nvgpu/common/gr/gr_setup.c @@ -99,7 +99,7 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, return -EINVAL; } - if (!g->ops.gr.is_valid_class(g, class_num)) { + if (!g->ops.class.is_valid(class_num)) { nvgpu_err(g, "invalid obj class 0x%x", class_num); err = -EINVAL; diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c index f8875d049..f570d75f0 100644 --- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c +++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c @@ -71,7 +71,7 @@ static int nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode(struct gk20a *g, nvgpu_log_fn(g, " "); if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP)) { - if (g->ops.gr.is_valid_compute_class(g, class)) { + if (g->ops.class.is_valid_compute(class)) { nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx, NVGPU_PREEMPTION_MODE_COMPUTE_CTA); } @@ -110,12 +110,12 @@ int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g, return 0; } - if (g->ops.gr.is_valid_gfx_class(g, class) && + if (g->ops.class.is_valid_gfx(class) && g->gr.ctx_vars.force_preemption_gfxp) { graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; } - if (g->ops.gr.is_valid_compute_class(g, class) && + if (g->ops.class.is_valid_compute(class) && g->gr.ctx_vars.force_preemption_cilp) { compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; } @@ -181,8 +181,8 @@ int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g, break; } - if (g->ops.gr.is_valid_compute_class(g, class) || - g->ops.gr.is_valid_gfx_class(g, class)) { + if (g->ops.class.is_valid_compute(class) || + g->ops.class.is_valid_gfx(class)) { switch (compute_preempt_mode) { case NVGPU_PREEMPTION_MODE_COMPUTE_WFI: case NVGPU_PREEMPTION_MODE_COMPUTE_CTA: diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 9a6cc5ab4..144772658 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -34,6 +34,7 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gm20b.h" #include "hal/regops/regops_gp10b.h" +#include "hal/class/class_gp10b.h" #include "hal/fifo/engines_gm20b.h" #include "hal/fifo/pbdma_gm20b.h" #include "hal/fifo/pbdma_gp10b.h" @@ -128,9 +129,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .handle_sw_method = NULL, .set_alpha_circular_buffer_size = NULL, .set_circular_buffer_size = NULL, - .is_valid_class = gr_gp10b_is_valid_class, - .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, - .is_valid_compute_class = gr_gp10b_is_valid_compute_class, .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, .set_hww_esr_report_mask = NULL, @@ -362,6 +360,11 @@ static const struct gpu_ops vgpu_gp10b_ops = { gp10b_gr_init_commit_cbes_reserve, }, }, + .class = { + .is_valid = gp10b_class_is_valid, + .is_valid_gfx = gp10b_class_is_valid_gfx, + .is_valid_compute = gp10b_class_is_valid_compute, + }, .perf = { .get_pmm_per_chiplet_offset = gm20b_perf_get_pmm_per_chiplet_offset, @@ -758,6 +761,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g) gops->cbc = vgpu_gp10b_ops.cbc; gops->ce2 = vgpu_gp10b_ops.ce2; gops->gr = vgpu_gp10b_ops.gr; + gops->class = vgpu_gp10b_ops.class; gops->gr.ctxsw_prog = vgpu_gp10b_ops.gr.ctxsw_prog; gops->gr.config = vgpu_gp10b_ops.gr.config; gops->fb = vgpu_gp10b_ops.fb; diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c index c9353eb9a..175e61447 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c @@ -230,7 +230,7 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) return -EINVAL; } - if (!g->ops.gr.is_valid_class(g, class_num)) { + if (!g->ops.class.is_valid(class_num)) { nvgpu_err(g, "invalid obj class 0x%x", class_num); err = -EINVAL; goto out; @@ -1248,10 +1248,10 @@ static int vgpu_gr_init_ctxsw_preemption_mode(struct gk20a *g, if (priv->constants.force_preempt_mode && !graphics_preempt_mode && !compute_preempt_mode) { - graphics_preempt_mode = g->ops.gr.is_valid_gfx_class(g, class) ? + graphics_preempt_mode = g->ops.class.is_valid_gfx(class) ? NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP : 0; compute_preempt_mode = - g->ops.gr.is_valid_compute_class(g, class) ? + g->ops.class.is_valid_compute(class) ? NVGPU_PREEMPTION_MODE_COMPUTE_CTA : 0; } @@ -1280,12 +1280,12 @@ static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g, &msg.params.gr_bind_ctxsw_buffers; int err = 0; - if (g->ops.gr.is_valid_gfx_class(g, class) && + if (g->ops.class.is_valid_gfx(class) && g->gr.ctx_vars.force_preemption_gfxp) { graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; } - if (g->ops.gr.is_valid_compute_class(g, class) && + if (g->ops.class.is_valid_compute(class) && g->gr.ctx_vars.force_preemption_cilp) { compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; } @@ -1369,7 +1369,7 @@ static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g, break; } - if (g->ops.gr.is_valid_compute_class(g, class)) { + if (g->ops.class.is_valid_compute(class)) { switch (compute_preempt_mode) { case NVGPU_PREEMPTION_MODE_COMPUTE_WFI: nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 9640cbb16..7e8fa3f02 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -23,6 +23,7 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gm20b.h" #include "hal/regops/regops_gv11b.h" +#include "hal/class/class_gv11b.h" #include "hal/fifo/engines_gv11b.h" #include "hal/fifo/pbdma_gm20b.h" #include "hal/fifo/pbdma_gp10b.h" @@ -151,9 +152,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .handle_sw_method = NULL, .set_alpha_circular_buffer_size = NULL, .set_circular_buffer_size = NULL, - .is_valid_class = gr_gv11b_is_valid_class, - .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, - .is_valid_compute_class = gr_gv11b_is_valid_compute_class, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, .set_hww_esr_report_mask = NULL, @@ -423,6 +421,11 @@ static const struct gpu_ops vgpu_gv11b_ops = { .handle_tex_exception = NULL, }, }, + .class = { + .is_valid = gv11b_class_is_valid, + .is_valid_gfx = gv11b_class_is_valid_gfx, + .is_valid_compute = gv11b_class_is_valid_compute, + }, .perf = { .get_pmm_per_chiplet_offset = gv11b_perf_get_pmm_per_chiplet_offset, @@ -845,6 +848,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g) gops->cbc = vgpu_gv11b_ops.cbc; gops->ce2 = vgpu_gv11b_ops.ce2; gops->gr = vgpu_gv11b_ops.gr; + gops->class = vgpu_gv11b_ops.class; gops->gr.ctxsw_prog = vgpu_gv11b_ops.gr.ctxsw_prog; gops->gr.config = vgpu_gv11b_ops.gr.config; gops->fb = vgpu_gv11b_ops.fb; diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 9bae026d5..5d587e73e 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -241,44 +242,6 @@ void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()); } -bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) -{ - bool valid = false; - - switch (class_num) { - case MAXWELL_COMPUTE_B: - case MAXWELL_B: - case FERMI_TWOD_A: - case KEPLER_DMA_COPY_A: - case MAXWELL_DMA_COPY_A: - valid = true; - break; - - default: - break; - } - - return valid; -} - -bool gr_gm20b_is_valid_gfx_class(struct gk20a *g, u32 class_num) -{ - if (class_num == MAXWELL_B) { - return true; - } else { - return false; - } -} - -bool gr_gm20b_is_valid_compute_class(struct gk20a *g, u32 class_num) -{ - if (class_num == MAXWELL_COMPUTE_B) { - return true; - } else { - return false; - } -} - /* Following are the blocks of registers that the ucode stores in the extended region.*/ diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 687e87c91..5ec0a0342 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -28,11 +28,7 @@ struct gk20a; struct nvgpu_warpstate; -#define MAXWELL_B 0xB197U -#define MAXWELL_COMPUTE_B 0xB1C0U -#define KEPLER_INLINE_TO_MEMORY_B 0xA140U -#define MAXWELL_DMA_COPY_A 0xB0B5U -#define MAXWELL_CHANNEL_GPFIFO_A 0xB06FU + #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 @@ -51,9 +47,6 @@ int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data); void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data); void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g); -bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num); -bool gr_gm20b_is_valid_gfx_class(struct gk20a *g, u32 class_num); -bool gr_gm20b_is_valid_compute_class(struct gk20a *g, u32 class_num); void gr_gm20b_init_sm_dsm_reg_info(void); void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, u32 *num_sm_dsm_perf_regs, diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 7e5eecac4..1538d4b29 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -23,6 +23,7 @@ */ #include #include +#include #include #include #include @@ -48,6 +49,7 @@ #include "hal/mc/mc_gm20b.h" #include "hal/bus/bus_gm20b.h" #include "hal/bus/bus_gk20a.h" +#include "hal/class/class_gm20b.h" #include "hal/priv_ring/priv_ring_gm20b.h" #include "hal/power_features/cg/gm20b_gating_reglist.h" #include "hal/cbc/cbc_gm20b.h" @@ -257,9 +259,6 @@ static const struct gpu_ops gm20b_ops = { .set_alpha_circular_buffer_size = gr_gm20b_set_alpha_circular_buffer_size, .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size, - .is_valid_class = gr_gm20b_is_valid_class, - .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class, - .is_valid_compute_class = gr_gm20b_is_valid_compute_class, .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, @@ -554,6 +553,11 @@ static const struct gpu_ops gm20b_ops = { gm20b_gr_falcon_fecs_host_int_enable, }, }, + .class = { + .is_valid = gm20b_class_is_valid, + .is_valid_gfx = gm20b_class_is_valid_gfx, + .is_valid_compute = gm20b_class_is_valid_compute, + }, .fb = { .init_hw = gm20b_fb_init_hw, .init_fs_state = fb_gm20b_init_fs_state, @@ -1033,6 +1037,7 @@ int gm20b_init_hal(struct gk20a *g) gops->cbc = gm20b_ops.cbc; gops->ce2 = gm20b_ops.ce2; gops->gr = gm20b_ops.gr; + gops->class = gm20b_ops.class; gops->gr.ctxsw_prog = gm20b_ops.gr.ctxsw_prog; gops->gr.config = gm20b_ops.gr.config; gops->fb = gm20b_ops.fb; diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index 23b906719..59779d8d7 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c @@ -22,6 +22,7 @@ * DEALINGS IN THE SOFTWARE. */ +#include #include #include #include @@ -37,35 +38,6 @@ #include -bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num) -{ - bool valid = false; - - switch (class_num) { - case PASCAL_COMPUTE_A: - case PASCAL_COMPUTE_B: - case PASCAL_A: - case PASCAL_B: - case PASCAL_DMA_COPY_A: - case PASCAL_DMA_COPY_B: - valid = true; - break; - - case MAXWELL_COMPUTE_B: - case MAXWELL_B: - case FERMI_TWOD_A: - case KEPLER_DMA_COPY_A: - case MAXWELL_DMA_COPY_A: - valid = true; - break; - - default: - break; - } - nvgpu_log_info(g, "class=0x%x valid=%d", class_num, valid); - return valid; -} - u32 gr_gp106_pagepool_default_size(struct gk20a *g) { return gr_scc_pagepool_total_pages_hwmax_value_v(); diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.h b/drivers/gpu/nvgpu/gp106/gr_gp106.h index 14a19aea5..2fe9f48a0 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.h @@ -27,10 +27,6 @@ struct gk20a; -#define PASCAL_B 0xC197U -#define PASCAL_COMPUTE_B 0xC1C0U - -bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num); u32 gr_gp106_pagepool_default_size(struct gk20a *g); int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 8dc33d563..db6844dc1 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -56,50 +57,6 @@ #define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000U -bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) -{ - bool valid = false; - - nvgpu_speculation_barrier(); - switch (class_num) { - case PASCAL_COMPUTE_A: - case PASCAL_A: - case PASCAL_DMA_COPY_A: - valid = true; - break; - - case MAXWELL_COMPUTE_B: - case MAXWELL_B: - case FERMI_TWOD_A: - case KEPLER_DMA_COPY_A: - case MAXWELL_DMA_COPY_A: - valid = true; - break; - - default: - break; - } - nvgpu_log_info(g, "class=0x%x valid=%d", class_num, valid); - return valid; -} - -bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num) -{ - if (class_num == PASCAL_A || class_num == MAXWELL_B) { - return true; - } else { - return false; - } -} - -bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num) -{ - if (class_num == PASCAL_COMPUTE_A || class_num == MAXWELL_COMPUTE_B) { - return true; - } else { - return false; - } -} static void gr_gp10b_sm_lrf_ecc_overcount_war(bool single_err, diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 0852637cb..b20afffce 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -33,12 +33,6 @@ struct nvgpu_gr_ctx; struct nvgpu_preemption_modes_rec; struct gk20a_debug_output; -#define PASCAL_CHANNEL_GPFIFO_A 0xC06FU -#define PASCAL_A 0xC097U -#define PASCAL_COMPUTE_A 0xC0C0U -#define PASCAL_DMA_COPY_A 0xC0B5U -#define PASCAL_DMA_COPY_B 0xC1B5U - #define NVC097_SET_GO_IDLE_TIMEOUT 0x022cU #define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU #define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028U @@ -61,9 +55,6 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g, int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk20a *fault_ch); -bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num); -bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num); -bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num); int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, bool *post_event, struct channel_gk20a *fault_ch, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 4a848b45b..0cedb9c85 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -23,6 +23,7 @@ */ #include #include +#include #include #include #include @@ -51,6 +52,7 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gm20b.h" #include "hal/bus/bus_gp10b.h" +#include "hal/class/class_gp10b.h" #include "hal/priv_ring/priv_ring_gm20b.h" #include "hal/priv_ring/priv_ring_gp10b.h" #include "hal/power_features/cg/gp10b_gating_reglist.h" @@ -291,9 +293,6 @@ static const struct gpu_ops gp10b_ops = { .set_alpha_circular_buffer_size = gr_gp10b_set_alpha_circular_buffer_size, .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size, - .is_valid_class = gr_gp10b_is_valid_class, - .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, - .is_valid_compute_class = gr_gp10b_is_valid_compute_class, .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, @@ -649,6 +648,11 @@ static const struct gpu_ops gp10b_ops = { gm20b_gr_falcon_fecs_host_int_enable, }, }, + .class = { + .is_valid = gp10b_class_is_valid, + .is_valid_gfx = gp10b_class_is_valid_gfx, + .is_valid_compute = gp10b_class_is_valid_compute, + }, .fb = { .init_hw = gm20b_fb_init_hw, .init_fs_state = fb_gm20b_init_fs_state, @@ -1139,6 +1143,7 @@ int gp10b_init_hal(struct gk20a *g) gops->cbc = gp10b_ops.cbc; gops->ce2 = gp10b_ops.ce2; gops->gr = gp10b_ops.gr; + gops->class = gp10b_ops.class; gops->gr.ctxsw_prog = gp10b_ops.gr.ctxsw_prog; gops->gr.config = gp10b_ops.gr.config; gops->fb = gp10b_ops.fb; diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 371b29e9b..593e228f0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -29,6 +29,7 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gp10b.h" #include "hal/bus/bus_gv100.h" +#include "hal/class/class_gv11b.h" #include "hal/priv_ring/priv_ring_gm20b.h" #include "hal/priv_ring/priv_ring_gp10b.h" #include "hal/power_features/cg/gv100_gating_reglist.h" @@ -158,6 +159,7 @@ #include "gv100/clk_gv100.h" #include +#include #include #include #include @@ -396,9 +398,6 @@ static const struct gpu_ops gv100_ops = { .set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size, .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, - .is_valid_class = gr_gv11b_is_valid_class, - .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, - .is_valid_compute_class = gr_gv11b_is_valid_compute_class, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, @@ -786,6 +785,11 @@ static const struct gpu_ops gv100_ops = { gv11b_gr_falcon_fecs_host_int_enable, }, }, + .class = { + .is_valid = gv11b_class_is_valid, + .is_valid_gfx = gv11b_class_is_valid_gfx, + .is_valid_compute = gv11b_class_is_valid_compute, + }, .fb = { .init_hw = gv11b_fb_init_hw, .init_fs_state = gp106_fb_init_fs_state, @@ -1423,6 +1427,7 @@ int gv100_init_hal(struct gk20a *g) gops->cbc = gv100_ops.cbc; gops->ce2 = gv100_ops.ce2; gops->gr = gv100_ops.gr; + gops->class = gv100_ops.class; gops->gr.ctxsw_prog = gv100_ops.gr.ctxsw_prog; gops->gr.config = gv100_ops.gr.config; gops->fb = gv100_ops.fb; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 85918a992..9315879eb 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -72,54 +73,6 @@ u32 gr_gv11b_ctxsw_checksum_mismatch_mailbox_val(void) return gr_fecs_ctxsw_mailbox_value_ctxsw_checksum_mismatch_v(); } -bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) -{ - bool valid = false; - - nvgpu_speculation_barrier(); - switch (class_num) { - case VOLTA_COMPUTE_A: - case VOLTA_A: - case VOLTA_DMA_COPY_A: - valid = true; - break; - - case MAXWELL_COMPUTE_B: - case MAXWELL_B: - case FERMI_TWOD_A: - case KEPLER_DMA_COPY_A: - case MAXWELL_DMA_COPY_A: - case PASCAL_COMPUTE_A: - case PASCAL_A: - case PASCAL_DMA_COPY_A: - valid = true; - break; - - default: - break; - } - nvgpu_log_info(g, "class=0x%x valid=%d", class_num, valid); - return valid; -} - -bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) -{ - bool valid = false; - - nvgpu_speculation_barrier(); - switch (class_num) { - case VOLTA_A: - case PASCAL_A: - case MAXWELL_B: - valid = true; - break; - - default: - break; - } - return valid; -} - void gr_gv11b_powergate_tpc(struct gk20a *g) { u32 tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); @@ -137,24 +90,6 @@ void gr_gv11b_powergate_tpc(struct gk20a *g) return; } -bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) -{ - bool valid = false; - - nvgpu_speculation_barrier(); - switch (class_num) { - case VOLTA_COMPUTE_A: - case PASCAL_COMPUTE_A: - case MAXWELL_COMPUTE_B: - valid = true; - break; - - default: - break; - } - return valid; -} - u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm) { diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 4d3dc32ad..bc94641d6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -39,11 +39,6 @@ struct gr_ctx_desc; struct nvgpu_gr_isr_data; struct gk20a_debug_output; -#define VOLTA_CHANNEL_GPFIFO_A 0xC36FU -#define VOLTA_A 0xC397U -#define VOLTA_COMPUTE_A 0xC3C0U -#define VOLTA_DMA_COPY_A 0xC3B5U - #define NVC397_SET_SHADER_EXCEPTIONS 0x1528U #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280U #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU @@ -74,9 +69,7 @@ struct gk20a_debug_output; void gr_gv11b_create_sysfs(struct gk20a *g); void gr_gv11b_remove_sysfs(struct gk20a *g); u32 gr_gv11b_ctxsw_checksum_mismatch_mailbox_val(void); -bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num); -bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num); -bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num); + int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e0fcb5e32..a044ec17f 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -22,6 +22,7 @@ * DEALINGS IN THE SOFTWARE. */ #include +#include #include #include #include @@ -35,6 +36,7 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gp10b.h" #include "hal/bus/bus_gm20b.h" +#include "hal/class/class_gv11b.h" #include "hal/priv_ring/priv_ring_gm20b.h" #include "hal/priv_ring/priv_ring_gp10b.h" #include "hal/gr/config/gr_config_gv100.h" @@ -360,9 +362,6 @@ static const struct gpu_ops gv11b_ops = { .set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size, .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, - .is_valid_class = gr_gv11b_is_valid_class, - .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, - .is_valid_compute_class = gr_gv11b_is_valid_compute_class, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, @@ -761,6 +760,11 @@ static const struct gpu_ops gv11b_ops = { gv11b_gr_falcon_fecs_host_int_enable, }, }, + .class = { + .is_valid = gv11b_class_is_valid, + .is_valid_gfx = gv11b_class_is_valid_gfx, + .is_valid_compute = gv11b_class_is_valid_compute, + }, .fb = { .init_hw = gv11b_fb_init_hw, .init_fs_state = gv11b_fb_init_fs_state, @@ -1312,6 +1316,7 @@ int gv11b_init_hal(struct gk20a *g) gops->cbc = gv11b_ops.cbc; gops->ce2 = gv11b_ops.ce2; gops->gr = gv11b_ops.gr; + gops->class = gv11b_ops.class; gops->gr.ctxsw_prog = gv11b_ops.gr.ctxsw_prog; gops->gr.config = gv11b_ops.gr.config; gops->fb = gv11b_ops.fb; diff --git a/drivers/gpu/nvgpu/hal/class/class_gm20b.c b/drivers/gpu/nvgpu/hal/class/class_gm20b.c new file mode 100644 index 000000000..55b43c76e --- /dev/null +++ b/drivers/gpu/nvgpu/hal/class/class_gm20b.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "class_gm20b.h" + +bool gm20b_class_is_valid(u32 class_num) +{ + bool valid = false; + + switch (class_num) { + case MAXWELL_COMPUTE_B: + case MAXWELL_B: + case FERMI_TWOD_A: + case KEPLER_DMA_COPY_A: + case MAXWELL_DMA_COPY_A: + valid = true; + break; + + default: + break; + } + + return valid; +} + +bool gm20b_class_is_valid_gfx(u32 class_num) +{ + if (class_num == MAXWELL_B) { + return true; + } else { + return false; + } +} + +bool gm20b_class_is_valid_compute(u32 class_num) +{ + if (class_num == MAXWELL_COMPUTE_B) { + return true; + } else { + return false; + } +} diff --git a/drivers/gpu/nvgpu/hal/class/class_gm20b.h b/drivers/gpu/nvgpu/hal/class/class_gm20b.h new file mode 100644 index 000000000..072028c8c --- /dev/null +++ b/drivers/gpu/nvgpu/hal/class/class_gm20b.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_CLASS_GM20B +#define NVGPU_CALSS_GM20B + +#include + +bool gm20b_class_is_valid(u32 class_num); +bool gm20b_class_is_valid_gfx(u32 class_num); +bool gm20b_class_is_valid_compute(u32 class_num); + +#endif diff --git a/drivers/gpu/nvgpu/hal/class/class_gp10b.c b/drivers/gpu/nvgpu/hal/class/class_gp10b.c new file mode 100644 index 000000000..4834ad6b0 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/class/class_gp10b.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include "class_gp10b.h" + +bool gp10b_class_is_valid(u32 class_num) +{ + bool valid = false; + + nvgpu_speculation_barrier(); + switch (class_num) { + case PASCAL_COMPUTE_A: + case PASCAL_A: + case PASCAL_DMA_COPY_A: + valid = true; + break; + + case MAXWELL_COMPUTE_B: + case MAXWELL_B: + case FERMI_TWOD_A: + case KEPLER_DMA_COPY_A: + case MAXWELL_DMA_COPY_A: + valid = true; + break; + + default: + break; + } + return valid; +} + +bool gp10b_class_is_valid_gfx(u32 class_num) +{ + if (class_num == PASCAL_A || class_num == MAXWELL_B) { + return true; + } else { + return false; + } +} + +bool gp10b_class_is_valid_compute(u32 class_num) +{ + if (class_num == PASCAL_COMPUTE_A || class_num == MAXWELL_COMPUTE_B) { + return true; + } else { + return false; + } +} diff --git a/drivers/gpu/nvgpu/hal/class/class_gp10b.h b/drivers/gpu/nvgpu/hal/class/class_gp10b.h new file mode 100644 index 000000000..6d5d4f152 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/class/class_gp10b.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_CLASS_GP10B +#define NVGPU_CALSS_GP10B + +#include + +bool gp10b_class_is_valid(u32 class_num); +bool gp10b_class_is_valid_gfx(u32 class_num); +bool gp10b_class_is_valid_compute(u32 class_num); + +#endif diff --git a/drivers/gpu/nvgpu/hal/class/class_gv11b.c b/drivers/gpu/nvgpu/hal/class/class_gv11b.c new file mode 100644 index 000000000..27fe0f2f1 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/class/class_gv11b.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include "class_gv11b.h" + +bool gv11b_class_is_valid(u32 class_num) +{ + bool valid = false; + + nvgpu_speculation_barrier(); + switch (class_num) { + case VOLTA_COMPUTE_A: + case VOLTA_A: + case VOLTA_DMA_COPY_A: + valid = true; + break; + + case MAXWELL_COMPUTE_B: + case MAXWELL_B: + case FERMI_TWOD_A: + case KEPLER_DMA_COPY_A: + case MAXWELL_DMA_COPY_A: + case PASCAL_COMPUTE_A: + case PASCAL_A: + case PASCAL_DMA_COPY_A: + valid = true; + break; + + default: + break; + } + return valid; +} + +bool gv11b_class_is_valid_gfx(u32 class_num) +{ + bool valid = false; + + nvgpu_speculation_barrier(); + switch (class_num) { + case VOLTA_A: + case PASCAL_A: + case MAXWELL_B: + valid = true; + break; + + default: + break; + } + return valid; +} + +bool gv11b_class_is_valid_compute(u32 class_num) +{ + bool valid = false; + + nvgpu_speculation_barrier(); + switch (class_num) { + case VOLTA_COMPUTE_A: + case PASCAL_COMPUTE_A: + case MAXWELL_COMPUTE_B: + valid = true; + break; + + default: + break; + } + return valid; +} diff --git a/drivers/gpu/nvgpu/hal/class/class_gv11b.h b/drivers/gpu/nvgpu/hal/class/class_gv11b.h new file mode 100644 index 000000000..06d9f7e65 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/class/class_gv11b.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_CLASS_GV11B +#define NVGPU_CALSS_GV11B + +#include + +bool gv11b_class_is_valid(u32 class_num); +bool gv11b_class_is_valid_gfx(u32 class_num); +bool gv11b_class_is_valid_compute(u32 class_num); + +#endif diff --git a/drivers/gpu/nvgpu/hal/class/class_tu104.c b/drivers/gpu/nvgpu/hal/class/class_tu104.c new file mode 100644 index 000000000..56e82c26b --- /dev/null +++ b/drivers/gpu/nvgpu/hal/class/class_tu104.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include "class_gv11b.h" +#include "class_tu104.h" + +bool tu104_class_is_valid(u32 class_num) +{ + nvgpu_speculation_barrier(); + switch (class_num) { + case TURING_CHANNEL_GPFIFO_A: + case TURING_A: + case TURING_COMPUTE_A: + case TURING_DMA_COPY_A: + return true; + default: + break; + } + + return gv11b_class_is_valid(class_num); +}; + +bool tu104_class_is_valid_gfx(u32 class_num) +{ + nvgpu_speculation_barrier(); + switch (class_num) { + case TURING_A: + return true; + default: + break; + } + + return gv11b_class_is_valid_gfx(class_num); +} + +bool tu104_class_is_valid_compute(u32 class_num) +{ + nvgpu_speculation_barrier(); + switch (class_num) { + case TURING_COMPUTE_A: + return true; + default: + break; + } + + return gv11b_class_is_valid_compute(class_num); +} diff --git a/drivers/gpu/nvgpu/hal/class/class_tu104.h b/drivers/gpu/nvgpu/hal/class/class_tu104.h new file mode 100644 index 000000000..72b10c0a3 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/class/class_tu104.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_CLASS_TU104 +#define NVGPU_CALSS_TU104 + +#include + +bool tu104_class_is_valid(u32 class_num); +bool tu104_class_is_valid_gfx(u32 class_num); +bool tu104_class_is_valid_compute(u32 class_num); + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/class.h b/drivers/gpu/nvgpu/include/nvgpu/class.h new file mode 100644 index 000000000..3bb1f827a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/class.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_CLASS_H +#define NVGPU_CLASS_H + +#define FERMI_TWOD_A 0x902DU +#define KEPLER_INLINE_TO_MEMORY_A 0xA040U +#define KEPLER_DMA_COPY_A 0xA0B5U + +#define MAXWELL_B 0xB197U +#define MAXWELL_COMPUTE_B 0xB1C0U +#define KEPLER_INLINE_TO_MEMORY_B 0xA140U +#define MAXWELL_DMA_COPY_A 0xB0B5U +#define MAXWELL_CHANNEL_GPFIFO_A 0xB06FU + +#define PASCAL_CHANNEL_GPFIFO_A 0xC06FU +#define PASCAL_A 0xC097U +#define PASCAL_COMPUTE_A 0xC0C0U +#define PASCAL_DMA_COPY_A 0xC0B5U +#define PASCAL_DMA_COPY_B 0xC1B5U + +#define PASCAL_B 0xC197U +#define PASCAL_COMPUTE_B 0xC1C0U + +#define VOLTA_CHANNEL_GPFIFO_A 0xC36FU +#define VOLTA_A 0xC397U +#define VOLTA_COMPUTE_A 0xC3C0U +#define VOLTA_DMA_COPY_A 0xC3B5U + +#define TURING_CHANNEL_GPFIFO_A 0xC46FU +#define TURING_A 0xC597U +#define TURING_COMPUTE_A 0xC5C0U +#define TURING_DMA_COPY_A 0xC5B5U + +#endif /* NVGPU_CLASS_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index b00a462b8..4fce66430 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -277,9 +277,6 @@ struct gpu_ops { void (*set_circular_buffer_size)(struct gk20a *g, u32 data); void (*set_bes_crop_debug3)(struct gk20a *g, u32 data); void (*set_bes_crop_debug4)(struct gk20a *g, u32 data); - bool (*is_valid_class)(struct gk20a *g, u32 class_num); - bool (*is_valid_gfx_class)(struct gk20a *g, u32 class_num); - bool (*is_valid_compute_class)(struct gk20a *g, u32 class_num); void (*get_sm_dsm_perf_regs)(struct gk20a *g, u32 *num_sm_dsm_perf_regs, u32 **sm_dsm_perf_regs, @@ -842,6 +839,13 @@ struct gpu_ops { void *data); } err_ops; } gr; + + struct { + bool (*is_valid)(u32 class_num); + bool (*is_valid_gfx)(u32 class_num); + bool (*is_valid_compute)(u32 class_num); + } class; + struct { void (*init_hw)(struct gk20a *g); void (*cbc_configure)(struct gk20a *g, struct nvgpu_cbc *cbc); @@ -2296,14 +2300,6 @@ void __gk20a_warn_on_no_regs(void); bool is_nvgpu_gpu_state_valid(struct gk20a *g); -/* classes that the device supports */ -/* TBD: get these from an open-sourced SDK? */ -enum { - FERMI_TWOD_A = 0x902D, - KEPLER_INLINE_TO_MEMORY_A = 0xA040, - KEPLER_DMA_COPY_A = 0xA0B5, -}; - #define GK20A_BAR0_IORESOURCE_MEM 0U #define GK20A_BAR1_IORESOURCE_MEM 1U #define GK20A_SIM_IORESOURCE_MEM 2U diff --git a/drivers/gpu/nvgpu/tu104/gr_tu104.c b/drivers/gpu/nvgpu/tu104/gr_tu104.c index 310f9fdad..cfc564ff4 100644 --- a/drivers/gpu/nvgpu/tu104/gr_tu104.c +++ b/drivers/gpu/nvgpu/tu104/gr_tu104.c @@ -21,6 +21,7 @@ */ #include +#include #include #include #include @@ -43,48 +44,6 @@ #include -bool gr_tu104_is_valid_class(struct gk20a *g, u32 class_num) -{ - nvgpu_speculation_barrier(); - switch (class_num) { - case TURING_CHANNEL_GPFIFO_A: - case TURING_A: - case TURING_COMPUTE_A: - case TURING_DMA_COPY_A: - return true; - default: - break; - } - - return gr_gv11b_is_valid_class(g, class_num); -}; - -bool gr_tu104_is_valid_gfx_class(struct gk20a *g, u32 class_num) -{ - nvgpu_speculation_barrier(); - switch (class_num) { - case TURING_A: - return true; - default: - break; - } - - return gr_gv11b_is_valid_gfx_class(g, class_num); -} - -bool gr_tu104_is_valid_compute_class(struct gk20a *g, u32 class_num) -{ - nvgpu_speculation_barrier(); - switch (class_num) { - case TURING_COMPUTE_A: - return true; - default: - break; - } - - return gr_gv11b_is_valid_compute_class(g, class_num); -} - int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g, enum ctxsw_addr_type addr_type, u32 num_tpcs, diff --git a/drivers/gpu/nvgpu/tu104/gr_tu104.h b/drivers/gpu/nvgpu/tu104/gr_tu104.h index 2ba85ced9..531743e73 100644 --- a/drivers/gpu/nvgpu/tu104/gr_tu104.h +++ b/drivers/gpu/nvgpu/tu104/gr_tu104.h @@ -29,11 +29,6 @@ struct gk20a; struct nvgpu_preemption_modes_rec; struct nvgpu_gr_ctx; -#define TURING_CHANNEL_GPFIFO_A 0xC46FU -#define TURING_A 0xC597U -#define TURING_COMPUTE_A 0xC5C0U -#define TURING_DMA_COPY_A 0xC5B5U - #define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528U #define NVC5C0_SET_SKEDCHECK 0x23cU #define NVC5C0_SET_SHADER_CUT_COLLECTOR 0x254U @@ -54,9 +49,7 @@ struct nvgpu_gr_ctx; #define NVC597_SET_SM_DISP_CTRL 0x10c8U #define NVC597_SET_SHADER_CUT_COLLECTOR 0x10d0U -bool gr_tu104_is_valid_class(struct gk20a *g, u32 class_num); -bool gr_tu104_is_valid_gfx_class(struct gk20a *g, u32 class_num); -bool gr_tu104_is_valid_compute_class(struct gk20a *g, u32 class_num); + int gr_tu104_init_sw_bundle64(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 87bf995e4..2c07f367d 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -31,6 +31,7 @@ #include "hal/bus/bus_gp10b.h" #include "hal/bus/bus_gv100.h" #include "hal/bus/bus_tu104.h" +#include "hal/class/class_tu104.h" #include "hal/priv_ring/priv_ring_gm20b.h" #include "hal/priv_ring/priv_ring_gp10b.h" #include "hal/power_features/cg/tu104_gating_reglist.h" @@ -181,6 +182,7 @@ #include #include #include +#include #include #include #include @@ -415,9 +417,6 @@ static const struct gpu_ops tu104_ops = { .set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size, .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, - .is_valid_class = gr_tu104_is_valid_class, - .is_valid_gfx_class = gr_tu104_is_valid_gfx_class, - .is_valid_compute_class = gr_tu104_is_valid_compute_class, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, .get_sm_dsm_perf_ctrl_regs = gr_tu104_get_sm_dsm_perf_ctrl_regs, .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, @@ -819,6 +818,11 @@ static const struct gpu_ops tu104_ops = { gv11b_gr_falcon_fecs_host_int_enable, }, }, + .class = { + .is_valid = tu104_class_is_valid, + .is_valid_gfx = tu104_class_is_valid_gfx, + .is_valid_compute = tu104_class_is_valid_compute, + }, .fb = { .init_hw = gv11b_fb_init_hw, .init_fs_state = gp106_fb_init_fs_state, @@ -1472,6 +1476,7 @@ int tu104_init_hal(struct gk20a *g) gops->cbc = tu104_ops.cbc; gops->ce2 = tu104_ops.ce2; gops->gr = tu104_ops.gr; + gops->class = tu104_ops.class; gops->gr.ctxsw_prog = tu104_ops.gr.ctxsw_prog; gops->gr.config = tu104_ops.gr.config; gops->fb = tu104_ops.fb;