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gpu: nvgpu: define gops.gr.init.set_default_compute_regs for Orin safety

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gops.gr.init.set_default_compute_regs() HAL configures compute specific
settings in safety build and this eliminates need of using SW methods.

Define this HAL for Orin safety build and configure sked check related
registers from the HAL. Other settings done on gv11b are no more
applicable for ga10b safety.

Bug 3456240

Change-Id: Ic125cdf414a5402511949015e3424b8cb2dab1e0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2646284
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2021-12-23 13:54:00 +05:30
committed by mobile promotions
parent b67a3cd053
commit 4fd0f11e9c
3 changed files with 26 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
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@@ -78,6 +78,10 @@ int ga10b_gr_init_wait_idle(struct gk20a *g);
void ga10b_gr_init_eng_config(struct gk20a *g); void ga10b_gr_init_eng_config(struct gk20a *g);
int ga10b_gr_init_reset_gpcs(struct gk20a *g); int ga10b_gr_init_reset_gpcs(struct gk20a *g);
int ga10b_gr_init_wait_empty(struct gk20a *g); int ga10b_gr_init_wait_empty(struct gk20a *g);
#ifndef CONFIG_NVGPU_NON_FUSA
void ga10b_gr_init_set_default_compute_regs(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx);
#endif
#ifdef CONFIG_NVGPU_MIG #ifdef CONFIG_NVGPU_MIG
bool ga10b_gr_init_is_allowed_reg(struct gk20a *g, u32 addr); bool ga10b_gr_init_is_allowed_reg(struct gk20a *g, u32 addr);
#endif #endif

19
drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b_fusa.c
View File

@@ -506,6 +506,25 @@ int ga10b_gr_init_wait_empty(struct gk20a *g)
return -EAGAIN; return -EAGAIN;
} }
#ifndef CONFIG_NVGPU_NON_FUSA
void ga10b_gr_init_set_default_compute_regs(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx)
{
u32 reg_val;
nvgpu_gr_ctx_patch_write_begin(g, gr_ctx, true);
reg_val = nvgpu_readl(g, gr_sked_hww_esr_en_r());
reg_val = set_field(reg_val,
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(),
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f());
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_sked_hww_esr_en_r(),
reg_val, true);
nvgpu_gr_ctx_patch_write_end(g, gr_ctx, true);
}
#endif
#ifdef CONFIG_NVGPU_MIG #ifdef CONFIG_NVGPU_MIG
bool ga10b_gr_init_is_allowed_reg(struct gk20a *g, u32 addr) bool ga10b_gr_init_is_allowed_reg(struct gk20a *g, u32 addr)
{ {

3
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -637,6 +637,9 @@ static const struct gops_gr_init ga10b_ops_gr_init = {
.get_max_subctx_count = gv11b_gr_init_get_max_subctx_count, .get_max_subctx_count = gv11b_gr_init_get_max_subctx_count,
.get_patch_slots = gv11b_gr_init_get_patch_slots, .get_patch_slots = gv11b_gr_init_get_patch_slots,
.detect_sm_arch = gv11b_gr_init_detect_sm_arch, .detect_sm_arch = gv11b_gr_init_detect_sm_arch,
#ifndef CONFIG_NVGPU_NON_FUSA
.set_default_compute_regs = ga10b_gr_init_set_default_compute_regs,
#endif
.get_supported__preemption_modes = gp10b_gr_init_get_supported_preemption_modes, .get_supported__preemption_modes = gp10b_gr_init_get_supported_preemption_modes,
.get_default_preemption_modes = gp10b_gr_init_get_default_preemption_modes, .get_default_preemption_modes = gp10b_gr_init_get_default_preemption_modes,
.is_allowed_sw_bundle = gm20b_gr_init_is_allowed_sw_bundle, .is_allowed_sw_bundle = gm20b_gr_init_is_allowed_sw_bundle,