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synced 2025-12-23 01:50:07 +03:00
gpu: nvgpu: os-agnostic segregation of sim/sim_pci
segregated os-agnostic function from linux/sim.c and linux/sim_pci.c to sim.c and sim_pci.c, while retaining os-specific functions. renamed all gk20a_* api's to nvgpu_*. renamed hw_sim_gk20a.h to nvgpu/hw_sim.h moved hw_sim_pci.h to nvgpu/hw_sim_pci.h JIRA VQRM-2368 Change-Id: I040a6b12b19111a0b99280245808ea2b0f344cdd Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702425 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
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mobile promotions
mobile promotions
parent
b144935644
commit
50d1b0c72b
@@ -23,254 +23,12 @@
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#include <nvgpu/bitops.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/hw_sim_pci.h>
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#include "gk20a/gk20a.h"
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#include "os_linux.h"
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#include "sim.h"
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#include "hw_sim_pci.h"
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static inline void sim_writel(struct sim_gk20a *sim, u32 r, u32 v)
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{
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struct sim_gk20a_linux *sim_linux =
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container_of(sim, struct sim_gk20a_linux, sim);
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writel(v, sim_linux->regs + r);
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}
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static inline u32 sim_readl(struct sim_gk20a *sim, u32 r)
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{
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struct sim_gk20a_linux *sim_linux =
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container_of(sim, struct sim_gk20a_linux, sim);
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return readl(sim_linux->regs + r);
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}
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static int gk20a_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem)
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{
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int err;
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err = nvgpu_dma_alloc(g, PAGE_SIZE, mem);
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if (err)
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return err;
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/*
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* create a valid cpu_va mapping
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*/
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nvgpu_mem_begin(g, mem);
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return 0;
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}
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static void gk20a_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem)
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{
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if (nvgpu_mem_is_valid(mem)) {
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/*
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* invalidate the cpu_va mapping
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*/
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nvgpu_mem_end(g, mem);
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nvgpu_dma_free(g, mem);
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}
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memset(mem, 0, sizeof(*mem));
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}
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static void gk20a_free_sim_support(struct gk20a *g)
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{
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gk20a_free_sim_buffer(g, &g->sim->send_bfr);
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gk20a_free_sim_buffer(g, &g->sim->recv_bfr);
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gk20a_free_sim_buffer(g, &g->sim->msg_bfr);
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}
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static void gk20a_remove_sim_support(struct sim_gk20a *s)
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{
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struct gk20a *g = s->g;
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struct sim_gk20a_linux *sim_linux =
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container_of(g->sim, struct sim_gk20a_linux, sim);
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if (sim_linux->regs)
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sim_writel(s, sim_config_r(), sim_config_mode_disabled_v());
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if (sim_linux->regs) {
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iounmap(sim_linux->regs);
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sim_linux->regs = NULL;
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}
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gk20a_free_sim_support(g);
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nvgpu_kfree(g, sim_linux);
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g->sim = NULL;
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}
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static inline u32 sim_msg_header_size(void)
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{
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return 32U;
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}
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static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
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{
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u8 *cpu_va;
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cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va;
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return (u32 *)(cpu_va + byte_offset);
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}
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static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
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{
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return sim_msg_bfr(g, byte_offset); /* starts at 0 */
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}
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static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
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{
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/* starts after msg header/cmn */
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return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
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}
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static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
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{
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*sim_msg_hdr(g, sim_msg_header_version_r()) =
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sim_msg_header_version_major_tot_v() |
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sim_msg_header_version_minor_tot_v();
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*sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v();
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*sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v();
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*sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v();
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*sim_msg_hdr(g, sim_msg_function_r()) = func;
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*sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size();
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}
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static inline u32 sim_escape_read_hdr_size(void)
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{
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return 12U;
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}
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static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
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{
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u8 *cpu_va;
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cpu_va = (u8 *)sim_linux->send_bfr.cpu_va;
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return (u32 *)(cpu_va + byte_offset);
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}
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static int rpc_send_message(struct gk20a *g)
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{
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/* calculations done in units of u32s */
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u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2;
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u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
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u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
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*sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
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sim_dma_target_phys_pci_coherent_f() |
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sim_dma_status_valid_f() |
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sim_dma_size_4kb_f() |
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sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT);
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*sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
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u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr));
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*sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
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g->sim->send_ring_put = (g->sim->send_ring_put + 2 * sizeof(u32)) %
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PAGE_SIZE;
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/* Update the put pointer. This will trap into the host. */
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sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
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return 0;
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}
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static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
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{
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u8 *cpu_va;
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cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va;
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return (u32 *)(cpu_va + byte_offset);
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}
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static int rpc_recv_poll(struct gk20a *g)
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{
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u64 recv_phys_addr;
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/* Poll the recv ring get pointer in an infinite loop */
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do {
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g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
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} while (g->sim->recv_ring_put == g->sim->recv_ring_get);
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/* process all replies */
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while (g->sim->recv_ring_put != g->sim->recv_ring_get) {
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/* these are in u32 offsets */
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u32 dma_lo_offset =
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sim_recv_put_pointer_v(g->sim->recv_ring_get)*2 + 0;
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u32 dma_hi_offset = dma_lo_offset + 1;
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u32 recv_phys_addr_lo = sim_dma_addr_lo_v(
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*sim_recv_ring_bfr(g, dma_lo_offset*4));
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u32 recv_phys_addr_hi = sim_dma_hi_addr_v(
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*sim_recv_ring_bfr(g, dma_hi_offset*4));
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recv_phys_addr = (u64)recv_phys_addr_hi << 32 |
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(u64)recv_phys_addr_lo << PAGE_SHIFT;
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if (recv_phys_addr !=
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nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) {
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nvgpu_err(g, "Error in RPC reply");
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return -EINVAL;
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}
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/* Update GET pointer */
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g->sim->recv_ring_get = (g->sim->recv_ring_get + 2*sizeof(u32))
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% PAGE_SIZE;
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sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
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g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
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}
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return 0;
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}
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static int issue_rpc_and_wait(struct gk20a *g)
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{
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int err;
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err = rpc_send_message(g);
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if (err) {
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nvgpu_err(g, "failed rpc_send_message");
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return err;
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}
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err = rpc_recv_poll(g);
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if (err) {
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nvgpu_err(g, "failed rpc_recv_poll");
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return err;
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}
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/* Now check if RPC really succeeded */
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if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) {
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nvgpu_err(g, "received failed status!");
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return -EINVAL;
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}
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return 0;
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}
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static int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data)
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{
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int err;
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size_t pathlen = strlen(path);
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u32 data_offset;
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sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
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sim_escape_read_hdr_size());
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*sim_msg_param(g, 0) = index;
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*sim_msg_param(g, 4) = sizeof(u32);
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data_offset = roundup(pathlen + 1, sizeof(u32));
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*sim_msg_param(g, 8) = data_offset;
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strcpy((char *)sim_msg_param(g, 0xc), path);
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err = issue_rpc_and_wait(g);
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if (!err)
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memcpy(data, sim_msg_param(g, data_offset + 0xc), sizeof(u32));
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return err;
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}
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#include "module.h"
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#include "sim.h" /* will be removed in subsequent patches */
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#include "sim_pci.h"/* will be removed in subsequent patches */
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static bool _nvgpu_pci_is_simulation(struct gk20a *g, u32 sim_base)
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{
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@@ -284,15 +42,39 @@ static bool _nvgpu_pci_is_simulation(struct gk20a *g, u32 sim_base)
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return is_simulation;
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}
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int nvgpu_pci_init_sim_support(struct gk20a *g)
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void nvgpu_remove_sim_support_linux_pci(struct gk20a *g)
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{
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int err = 0;
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u64 phys;
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struct sim_gk20a_linux *sim_linux;
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struct sim_nvgpu_linux *sim_linux;
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bool is_simulation;
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is_simulation = _nvgpu_pci_is_simulation(g, sim_r());
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if (!is_simulation) {
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nvgpu_warn(g, "not in sim_mode");
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return;
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}
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if (!g->sim) {
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nvgpu_warn(g, "sim_gk20a not allocated");
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return;
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}
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sim_linux = container_of(g->sim, struct sim_nvgpu_linux, sim);
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if (sim_linux->regs) {
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sim_writel(g->sim, sim_config_r(), sim_config_mode_disabled_v());
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sim_linux->regs = NULL;
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}
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nvgpu_kfree(g, sim_linux);
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g->sim = NULL;
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}
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int nvgpu_init_sim_support_linux_pci(struct gk20a *g)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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struct sim_nvgpu_linux *sim_linux;
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int err = -ENOMEM;
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bool is_simulation;
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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/* initialize sim aperture */
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is_simulation = _nvgpu_pci_is_simulation(g, sim_r());
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__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, is_simulation);
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@@ -301,57 +83,11 @@ int nvgpu_pci_init_sim_support(struct gk20a *g)
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sim_linux = nvgpu_kzalloc(g, sizeof(*sim_linux));
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if (!sim_linux)
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goto fail;
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return err;
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g->sim = &sim_linux->sim;
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g->sim->g = g;
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sim_linux->regs = l->regs + sim_r();
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sim_linux->remove_support_linux = nvgpu_remove_sim_support_linux_pci;
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/* allocate sim event/msg buffers */
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err = gk20a_alloc_sim_buffer(g, &g->sim->send_bfr);
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err = err || gk20a_alloc_sim_buffer(g, &g->sim->recv_bfr);
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err = err || gk20a_alloc_sim_buffer(g, &g->sim->msg_bfr);
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if (err)
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goto fail;
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/* mark send ring invalid */
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sim_writel(g->sim, sim_send_ring_r(), sim_send_ring_status_invalid_f());
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/* read get pointer and make equal to put */
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g->sim->send_ring_put = sim_readl(g->sim, sim_send_get_r());
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sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
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/* write send ring address and make it valid */
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phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr);
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sim_writel(g->sim, sim_send_ring_hi_r(),
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sim_send_ring_hi_addr_f(u64_hi32(phys)));
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sim_writel(g->sim, sim_send_ring_r(),
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sim_send_ring_status_valid_f() |
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sim_send_ring_target_phys_pci_coherent_f() |
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sim_send_ring_size_4kb_f() |
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sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT));
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/* repeat for recv ring (but swap put,get as roles are opposite) */
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sim_writel(g->sim, sim_recv_ring_r(), sim_recv_ring_status_invalid_f());
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/* read put pointer and make equal to get */
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g->sim->recv_ring_get = sim_readl(g->sim, sim_recv_put_r());
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sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
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/* write send ring address and make it valid */
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phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr);
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sim_writel(g->sim, sim_recv_ring_hi_r(),
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sim_recv_ring_hi_addr_f(u64_hi32(phys)));
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sim_writel(g->sim, sim_recv_ring_r(),
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sim_recv_ring_status_valid_f() |
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sim_recv_ring_target_phys_pci_coherent_f() |
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sim_recv_ring_size_4kb_f() |
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sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT));
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g->sim->remove_support = gk20a_remove_sim_support;
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g->sim->esc_readl = gk20a_sim_esc_readl;
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return 0;
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fail:
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gk20a_free_sim_support(g);
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return err;
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}
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