From 50d4421dc2bc4135d0e52cf06e24db64de833ad8 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 9 May 2019 12:45:15 -0700 Subject: [PATCH] gpu: nvgpu: fifo MISRA fix for Rule 10.3 JIRA NVGPU-3383 Change-Id: Ic1b30cd4b8c5dba0ea75ff0de316d0d5dcc99ae4 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/2116730 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c index 9823a7f01..96956870e 100644 --- a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c +++ b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c @@ -83,7 +83,7 @@ static inline u32 gm20b_engine_id_to_fault_id(struct gk20a *g, void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, unsigned long engine_ids_bitmask) { - unsigned long poll_delay = POLL_DELAY_MIN_US; + unsigned int poll_delay = POLL_DELAY_MIN_US; unsigned long engine_id; int ret; struct nvgpu_timeout timeout; @@ -119,8 +119,8 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, break; } - nvgpu_usleep_range(poll_delay, poll_delay * 2UL); - poll_delay = min_t(u32, poll_delay << 1, POLL_DELAY_MAX_US); + nvgpu_usleep_range(poll_delay, poll_delay * 2U); + poll_delay = min_t(u32, poll_delay << 1U, POLL_DELAY_MAX_US); } while (nvgpu_timeout_expired(&timeout) == 0); if (ret != 0) { @@ -129,6 +129,6 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, /* release trigger mmu fault */ for_each_set_bit(engine_id, &engine_ids_bitmask, 32UL) { - nvgpu_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); + nvgpu_writel(g, fifo_trigger_mmu_fault_r((u32)engine_id), 0U); } }