From 50d9eb15543a31dbf0e038c2f3c99aa80e73da4a Mon Sep 17 00:00:00 2001 From: Srirangan Madhavan Date: Tue, 20 Nov 2018 10:40:43 +0530 Subject: [PATCH] gpu: nvgpu: Fix MISRA 12.2 misc bit shift errors MISRA rule 12.2 states that the right hand operand of a shift operator shall lie in the range zero to one less than the width in bits of the essential type of the left hand operand. This patch will fix these violations in posix code by casting them to an appropriate type or using the relevant BITxx() macros. JIRA NVGPU-666 Change-Id: Ibc428ee71977685f413ca0f972efeff34268da62 Signed-off-by: Srirangan Madhavan Reviewed-on: https://git-master.nvidia.com/r/1954303 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sagar Kamble Reviewed-by: Konsta Holtta Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/timers.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/timers.h b/drivers/gpu/nvgpu/include/nvgpu/timers.h index f69e23499..899344cc9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/timers.h +++ b/drivers/gpu/nvgpu/include/nvgpu/timers.h @@ -74,8 +74,8 @@ struct nvgpu_timeout { /* * Bits 1 through 7 are reserved; bits 8 and up are flags: */ -#define NVGPU_TIMER_NO_PRE_SI (0x1 << 8) -#define NVGPU_TIMER_SILENT_TIMEOUT (0x1 << 9) +#define NVGPU_TIMER_NO_PRE_SI BIT32(8) +#define NVGPU_TIMER_SILENT_TIMEOUT BIT32(9) #define NVGPU_TIMER_FLAG_MASK (NVGPU_TIMER_RETRY_TIMER | \ NVGPU_TIMER_NO_PRE_SI | \