From 510b6cc8b2a7b2fd481b1d06ded69ca273a56f64 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 2 May 2019 15:38:32 +0530 Subject: [PATCH] gpu: nvgpu: fix MISRA 15.7 violation in gr.config unit Below MISRA 15.7 violation is reported in common.gr.config unit nvgpu/drivers/gpu/nvgpu/common/gr/gr_config.c:169: misra_violation: No non-empty terminating "else" statement. Fix this by adding terminating "else" statement Jira NVGPU-3225 Change-Id: Iaec3d6595da8fca55dfad8a8ccbcbad2ba7b1fe1 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2110987 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr_config.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr_config.c b/drivers/gpu/nvgpu/common/gr/gr_config.c index f0ef8f74b..2644900d5 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_config.c +++ b/drivers/gpu/nvgpu/common/gr/gr_config.c @@ -165,7 +165,6 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) config->ppc_count += config->gpc_ppc_count[gpc_index]; - gpc_new_skip_mask = 0; if (config->pe_count_per_gpc > 1U && config->pes_tpc_count[0][gpc_index] + config->pes_tpc_count[1][gpc_index] == 5U) { @@ -191,6 +190,8 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) config->pes_tpc_mask[pes_heavy_index][gpc_index] ^ (config->pes_tpc_mask[pes_heavy_index][gpc_index] & (config->pes_tpc_mask[pes_heavy_index][gpc_index] - 1U)); + } else { + gpc_new_skip_mask = 0U; } config->gpc_skip_mask[gpc_index] = gpc_new_skip_mask; }