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synced 2025-12-25 11:04:51 +03:00
gpu: nvgpu: gv11b: hw header update
Updated hw headers to CL#37001916. Some of important changes include new door bell user mode mechanism and new runlist structure. Bug 1735765 Change-Id: Icf01156dd3e7d94466f553ffc53267e4043e1188 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1205888 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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seshendra Gadagottu
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@@ -72,16 +72,16 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
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gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
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/* Check for LRF ECC errors. */
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lrf_ecc_status = gk20a_readl(g,
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset);
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if ( (lrf_ecc_status &
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lrf_ecc_status = gk20a_readl(g,
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset);
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if ((lrf_ecc_status &
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) ||
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(lrf_ecc_status &
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) ||
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(lrf_ecc_status &
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) ||
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(lrf_ecc_status &
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()) ) {
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f())) {
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
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"Single bit error detected in SM LRF!");
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@@ -93,14 +93,14 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
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gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset,
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0);
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}
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if ( (lrf_ecc_status &
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if ((lrf_ecc_status &
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) ||
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(lrf_ecc_status &
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) ||
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(lrf_ecc_status &
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) ||
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(lrf_ecc_status &
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()) ) {
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gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f())) {
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
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"Double bit error detected in SM LRF!");
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@@ -109,14 +109,13 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
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gk20a_readl(g,
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gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset);
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gk20a_writel(g,
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gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset,
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0);
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gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, 0);
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}
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gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset,
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lrf_ecc_status);
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/* Check for SHM ECC errors. */
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shm_ecc_status = gk20a_readl(g,
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shm_ecc_status = gk20a_readl(g,
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gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset);
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if ((shm_ecc_status &
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gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) ||
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@@ -125,7 +124,7 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
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(shm_ecc_status &
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gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) ||
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(shm_ecc_status &
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gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) {
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gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f())) {
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u32 ecc_stats_reg_val;
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
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@@ -144,10 +143,10 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
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gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
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ecc_stats_reg_val);
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}
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if ( (shm_ecc_status &
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if ((shm_ecc_status &
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gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) ||
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(shm_ecc_status &
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gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) {
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gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f())) {
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u32 ecc_stats_reg_val;
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
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@@ -1133,8 +1132,8 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
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gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r()));
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gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n",
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gk20a_readl(g, gr_cwd_fs_r()));
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gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n",
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gk20a_readl(g, gr_fe_tpc_fs_r()));
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gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS(0): 0x%x\n",
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gk20a_readl(g, gr_fe_tpc_fs_r(0)));
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gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n",
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gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0)));
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gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n",
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@@ -1184,7 +1183,7 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
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static bool gr_activity_empty_or_preempted(u32 val)
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{
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while(val) {
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while (val) {
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u32 v = val & 7;
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if (v != gr_activity_4_gpc0_empty_v() &&
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v != gr_activity_4_gpc0_preempted_v())
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@@ -1542,16 +1541,16 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
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gpc, tpc, global_esr);
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if (cilp_enabled && sm_debugger_attached) {
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if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f())
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gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
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gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f());
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if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f())
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gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset,
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gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f());
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if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f())
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gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
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gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f());
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if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f())
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gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset,
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gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f());
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global_mask = gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() |
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gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f();
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global_mask = gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f() |
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gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f();
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if (warp_esr != 0 || (global_esr & global_mask) != 0) {
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*ignore_debugger = true;
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@@ -1575,7 +1574,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
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}
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/* reset the HWW errors after locking down */
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global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset);
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global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset);
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gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy);
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
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"CILP: HWWs cleared for gpc %d tpc %d\n",
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@@ -1588,15 +1587,15 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
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return ret;
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}
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dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset);
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if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) {
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dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset);
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if (dbgr_control0 & gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f()) {
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
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"CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n",
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gpc, tpc);
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dbgr_control0 = set_field(dbgr_control0,
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gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(),
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gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f());
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gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0);
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gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(),
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gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f());
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gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, dbgr_control0);
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}
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
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@@ -1703,10 +1702,10 @@ clean_up:
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static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr)
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{
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if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m()))
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if (!(hww_warp_esr & gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m()))
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hww_warp_esr = set_field(hww_warp_esr,
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gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(),
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gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f());
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gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(),
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gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f());
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return hww_warp_esr;
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}
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@@ -50,6 +50,30 @@
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#ifndef _hw_bus_gv11b_h_
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#define _hw_bus_gv11b_h_
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static inline u32 bus_bar0_window_r(void)
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{
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return 0x00001700;
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}
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static inline u32 bus_bar0_window_base_f(u32 v)
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{
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return (v & 0xffffff) << 0;
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}
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static inline u32 bus_bar0_window_target_vid_mem_f(void)
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{
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return 0x0;
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}
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static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
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{
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return 0x2000000;
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}
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static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
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{
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return 0x3000000;
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}
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static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
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{
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return 0x00000010;
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}
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static inline u32 bus_bar1_block_r(void)
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{
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return 0x00001704;
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@@ -174,18 +174,6 @@ static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
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{
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return 0x10;
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}
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static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
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{
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return 0x18;
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}
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static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
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{
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return 0x20;
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}
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static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
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{
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return 0x20;
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}
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static inline u32 fb_mmu_invalidate_sys_membar_s(void)
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{
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return 1;
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@@ -104,7 +104,7 @@ static inline u32 fifo_eng_runlist_base_r(u32 i)
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}
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static inline u32 fifo_eng_runlist_base__size_1_v(void)
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{
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return 0x00000001;
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return 0x00000002;
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}
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static inline u32 fifo_eng_runlist_r(u32 i)
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{
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@@ -112,7 +112,7 @@ static inline u32 fifo_eng_runlist_r(u32 i)
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}
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static inline u32 fifo_eng_runlist__size_1_v(void)
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{
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return 0x00000001;
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return 0x00000002;
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}
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static inline u32 fifo_eng_runlist_length_f(u32 v)
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{
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@@ -268,7 +268,7 @@ static inline u32 fifo_intr_mmu_fault_id_r(void)
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}
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static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
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{
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return 0x00000000;
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return 0x00000040;
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}
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static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
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{
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@@ -332,7 +332,7 @@ static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
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}
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static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
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{
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return 0x00000001;
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return 0x00000003;
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}
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static inline u32 fifo_intr_runlist_r(void)
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{
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@@ -412,7 +412,7 @@ static inline u32 fifo_engine_status_r(u32 i)
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}
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static inline u32 fifo_engine_status__size_1_v(void)
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{
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return 0x00000002;
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return 0x00000004;
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}
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static inline u32 fifo_engine_status_id_v(u32 r)
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{
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@@ -500,7 +500,7 @@ static inline u32 fifo_pbdma_status_r(u32 i)
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}
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static inline u32 fifo_pbdma_status__size_1_v(void)
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{
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return 0x00000001;
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return 0x00000003;
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}
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static inline u32 fifo_pbdma_status_id_v(u32 r)
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{
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@@ -600,11 +600,11 @@ static inline u32 fifo_replay_fault_buffer_size_r(void)
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}
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static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
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{
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return (v & 0x1ff) << 0;
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return (v & 0x3ff) << 0;
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}
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static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
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{
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return 0x000000c0;
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return 0x00000140;
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}
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static inline u32 fifo_replay_fault_buffer_get_r(void)
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{
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@@ -612,7 +612,7 @@ static inline u32 fifo_replay_fault_buffer_get_r(void)
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}
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static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
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{
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return (v & 0x1ff) << 0;
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return (v & 0x3ff) << 0;
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}
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static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
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{
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@@ -624,7 +624,7 @@ static inline u32 fifo_replay_fault_buffer_put_r(void)
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}
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static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
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{
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return (v & 0x1ff) << 0;
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return (v & 0x3ff) << 0;
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}
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static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
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{
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@@ -242,6 +242,14 @@ static inline u32 gmmu_new_pte_address_sys_w(void)
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{
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return 0;
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}
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static inline u32 gmmu_new_pte_address_vid_f(u32 v)
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{
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return (v & 0xffffff) << 8;
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}
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static inline u32 gmmu_new_pte_address_vid_w(void)
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{
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return 0;
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}
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static inline u32 gmmu_new_pte_vol_w(void)
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{
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return 0;
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@@ -1110,7 +1118,7 @@ static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
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{
|
||||
return 0x000000de;
|
||||
}
|
||||
static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
|
||||
static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void)
|
||||
{
|
||||
return 0x000000cc;
|
||||
}
|
||||
@@ -1174,7 +1182,7 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
|
||||
{
|
||||
return 0x000000ec;
|
||||
}
|
||||
static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
|
||||
static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void)
|
||||
{
|
||||
return 0x000000cd;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -570,12 +570,4 @@ static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
|
||||
{
|
||||
return (r >> 16) & 0x1f;
|
||||
}
|
||||
static inline u32 ltc_ltca_g_axi_pctrl_r(void)
|
||||
{
|
||||
return 0x00160000;
|
||||
}
|
||||
static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 2;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -72,7 +72,7 @@ static inline u32 pbdma_gp_base_r(u32 i)
|
||||
}
|
||||
static inline u32 pbdma_gp_base__size_1_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
return 0x00000003;
|
||||
}
|
||||
static inline u32 pbdma_gp_base_offset_f(u32 v)
|
||||
{
|
||||
@@ -470,10 +470,6 @@ static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
|
||||
{
|
||||
return 0x80000;
|
||||
}
|
||||
static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
|
||||
{
|
||||
return 0x100000;
|
||||
}
|
||||
static inline u32 pbdma_intr_0_method_pending_f(void)
|
||||
{
|
||||
return 0x200000;
|
||||
@@ -510,10 +506,6 @@ static inline u32 pbdma_intr_0_signature_pending_f(void)
|
||||
{
|
||||
return 0x80000000;
|
||||
}
|
||||
static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void)
|
||||
{
|
||||
return 0x10000000;
|
||||
}
|
||||
static inline u32 pbdma_intr_1_r(u32 i)
|
||||
{
|
||||
return 0x00040148 + i*8192;
|
||||
@@ -566,38 +558,6 @@ static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v)
|
||||
{
|
||||
return (v & 0x7fff) << 0;
|
||||
}
|
||||
static inline u32 pbdma_syncpointa_r(u32 i)
|
||||
{
|
||||
return 0x000400a4 + i*8192;
|
||||
}
|
||||
static inline u32 pbdma_syncpointa_payload_v(u32 r)
|
||||
{
|
||||
return (r >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline u32 pbdma_syncpointb_r(u32 i)
|
||||
{
|
||||
return 0x000400a8 + i*8192;
|
||||
}
|
||||
static inline u32 pbdma_syncpointb_op_v(u32 r)
|
||||
{
|
||||
return (r >> 0) & 0x1;
|
||||
}
|
||||
static inline u32 pbdma_syncpointb_op_wait_v(void)
|
||||
{
|
||||
return 0x00000000;
|
||||
}
|
||||
static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
|
||||
{
|
||||
return (r >> 4) & 0x1;
|
||||
}
|
||||
static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
}
|
||||
static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
|
||||
{
|
||||
return (r >> 8) & 0xfff;
|
||||
}
|
||||
static inline u32 pbdma_runlist_timeslice_r(u32 i)
|
||||
{
|
||||
return 0x000400f8 + i*8192;
|
||||
|
||||
@@ -52,7 +52,7 @@
|
||||
|
||||
static inline u32 perf_pmasys_control_r(void)
|
||||
{
|
||||
return 0x001b4000;
|
||||
return 0x0024a000;
|
||||
}
|
||||
static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
|
||||
{
|
||||
@@ -84,7 +84,7 @@ static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
|
||||
}
|
||||
static inline u32 perf_pmasys_mem_block_r(void)
|
||||
{
|
||||
return 0x001b4070;
|
||||
return 0x0024a070;
|
||||
}
|
||||
static inline u32 perf_pmasys_mem_block_base_f(u32 v)
|
||||
{
|
||||
@@ -148,7 +148,7 @@ static inline u32 perf_pmasys_mem_block_valid_false_f(void)
|
||||
}
|
||||
static inline u32 perf_pmasys_outbase_r(void)
|
||||
{
|
||||
return 0x001b4074;
|
||||
return 0x0024a074;
|
||||
}
|
||||
static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
|
||||
{
|
||||
@@ -156,7 +156,7 @@ static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
|
||||
}
|
||||
static inline u32 perf_pmasys_outbaseupper_r(void)
|
||||
{
|
||||
return 0x001b4078;
|
||||
return 0x0024a078;
|
||||
}
|
||||
static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
|
||||
{
|
||||
@@ -164,7 +164,7 @@ static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
|
||||
}
|
||||
static inline u32 perf_pmasys_outsize_r(void)
|
||||
{
|
||||
return 0x001b407c;
|
||||
return 0x0024a07c;
|
||||
}
|
||||
static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
|
||||
{
|
||||
@@ -172,7 +172,7 @@ static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
|
||||
}
|
||||
static inline u32 perf_pmasys_mem_bytes_r(void)
|
||||
{
|
||||
return 0x001b4084;
|
||||
return 0x0024a084;
|
||||
}
|
||||
static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
|
||||
{
|
||||
@@ -180,7 +180,7 @@ static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
|
||||
}
|
||||
static inline u32 perf_pmasys_mem_bump_r(void)
|
||||
{
|
||||
return 0x001b4088;
|
||||
return 0x0024a088;
|
||||
}
|
||||
static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
|
||||
{
|
||||
@@ -188,7 +188,7 @@ static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
|
||||
}
|
||||
static inline u32 perf_pmasys_enginestatus_r(void)
|
||||
{
|
||||
return 0x001b40a4;
|
||||
return 0x0024a0a4;
|
||||
}
|
||||
static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
|
||||
{
|
||||
|
||||
@@ -108,23 +108,23 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void)
|
||||
}
|
||||
static inline u32 proj_host_num_engines_v(void)
|
||||
{
|
||||
return 0x00000002;
|
||||
return 0x00000004;
|
||||
}
|
||||
static inline u32 proj_host_num_pbdma_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
return 0x00000003;
|
||||
}
|
||||
static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
|
||||
{
|
||||
return 0x00000002;
|
||||
return 0x00000004;
|
||||
}
|
||||
static inline u32 proj_scal_litter_num_fbps_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
return 0x00000002;
|
||||
}
|
||||
static inline u32 proj_scal_litter_num_fbpas_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
return 0x00000004;
|
||||
}
|
||||
static inline u32 proj_scal_litter_num_gpcs_v(void)
|
||||
{
|
||||
@@ -132,7 +132,7 @@ static inline u32 proj_scal_litter_num_gpcs_v(void)
|
||||
}
|
||||
static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
return 0x00000002;
|
||||
}
|
||||
static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
|
||||
{
|
||||
|
||||
@@ -608,11 +608,11 @@ static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
|
||||
}
|
||||
static inline u32 pwr_pmu_queue_head_r(u32 i)
|
||||
{
|
||||
return 0x0010a4a0 + i*4;
|
||||
return 0x0010a800 + i*4;
|
||||
}
|
||||
static inline u32 pwr_pmu_queue_head__size_1_v(void)
|
||||
{
|
||||
return 0x00000004;
|
||||
return 0x00000008;
|
||||
}
|
||||
static inline u32 pwr_pmu_queue_head_address_f(u32 v)
|
||||
{
|
||||
@@ -624,11 +624,11 @@ static inline u32 pwr_pmu_queue_head_address_v(u32 r)
|
||||
}
|
||||
static inline u32 pwr_pmu_queue_tail_r(u32 i)
|
||||
{
|
||||
return 0x0010a4b0 + i*4;
|
||||
return 0x0010a820 + i*4;
|
||||
}
|
||||
static inline u32 pwr_pmu_queue_tail__size_1_v(void)
|
||||
{
|
||||
return 0x00000004;
|
||||
return 0x00000008;
|
||||
}
|
||||
static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
|
||||
{
|
||||
|
||||
@@ -148,7 +148,7 @@ static inline u32 ram_in_page_dir_base_lo_w(void)
|
||||
}
|
||||
static inline u32 ram_in_page_dir_base_hi_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 0;
|
||||
return (v & 0xffffffff) << 0;
|
||||
}
|
||||
static inline u32 ram_in_page_dir_base_hi_w(void)
|
||||
{
|
||||
@@ -354,14 +354,6 @@ static inline u32 ram_fc_allowed_syncpoints_w(void)
|
||||
{
|
||||
return 58;
|
||||
}
|
||||
static inline u32 ram_fc_syncpointa_w(void)
|
||||
{
|
||||
return 41;
|
||||
}
|
||||
static inline u32 ram_fc_syncpointb_w(void)
|
||||
{
|
||||
return 42;
|
||||
}
|
||||
static inline u32 ram_fc_target_w(void)
|
||||
{
|
||||
return 43;
|
||||
@@ -443,6 +435,74 @@ static inline u32 ram_userd_gp_top_level_get_hi_w(void)
|
||||
return 23;
|
||||
}
|
||||
static inline u32 ram_rl_entry_size_v(void)
|
||||
{
|
||||
return 0x00000010;
|
||||
}
|
||||
static inline u32 ram_rl_entry_type_f(u32 v)
|
||||
{
|
||||
return (v & 0x1) << 0;
|
||||
}
|
||||
static inline u32 ram_rl_entry_type_channel_v(void)
|
||||
{
|
||||
return 0x00000000;
|
||||
}
|
||||
static inline u32 ram_rl_entry_type_tsg_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
}
|
||||
static inline u32 ram_rl_entry_id_f(u32 v)
|
||||
{
|
||||
return (v & 0xfff) << 0;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v)
|
||||
{
|
||||
return (v & 0x1) << 1;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_inst_target_f(u32 v)
|
||||
{
|
||||
return (v & 0x3) << 4;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_inst_target_target_sys_mem_ncoh_v(void)
|
||||
{
|
||||
return 0x00000003;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_target_f(u32 v)
|
||||
{
|
||||
return (v & 0x3) << 6;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_v(void)
|
||||
{
|
||||
return 0x00000000;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_nvlink_coh_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_coh_v(void)
|
||||
{
|
||||
return 0x00000002;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_ncoh_v(void)
|
||||
{
|
||||
return 0x00000003;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v)
|
||||
{
|
||||
return (v & 0xffffff) << 8;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v)
|
||||
{
|
||||
return (v & 0xffffffff) << 0;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_inst_ptr_align_shift_v(void)
|
||||
{
|
||||
return 0x0000000c;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_ptr_align_shift_v(void)
|
||||
{
|
||||
return 0x00000008;
|
||||
}
|
||||
static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_align_shift_v(void)
|
||||
{
|
||||
return 0x00000008;
|
||||
}
|
||||
@@ -450,40 +510,56 @@ static inline u32 ram_rl_entry_chid_f(u32 v)
|
||||
{
|
||||
return (v & 0xfff) << 0;
|
||||
}
|
||||
static inline u32 ram_rl_entry_id_f(u32 v)
|
||||
static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v)
|
||||
{
|
||||
return (v & 0xfff) << 0;
|
||||
return (v & 0xfffff) << 12;
|
||||
}
|
||||
static inline u32 ram_rl_entry_type_f(u32 v)
|
||||
static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v)
|
||||
{
|
||||
return (v & 0x1) << 13;
|
||||
return (v & 0xffffffff) << 0;
|
||||
}
|
||||
static inline u32 ram_rl_entry_type_chid_f(void)
|
||||
static inline u32 ram_rl_entry_tsg_vmid_f(u32 v)
|
||||
{
|
||||
return 0x0;
|
||||
return (v & 0xff) << 4;
|
||||
}
|
||||
static inline u32 ram_rl_entry_type_tsg_f(void)
|
||||
static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v)
|
||||
{
|
||||
return 0x2000;
|
||||
return (v & 0xf) << 16;
|
||||
}
|
||||
static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
|
||||
static inline u32 ram_rl_entry_tsg_timeslice_scale_entry_tsg_timeslice_scale_3_v(void)
|
||||
{
|
||||
return (v & 0xf) << 14;
|
||||
return 0x00000003;
|
||||
}
|
||||
static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
|
||||
static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v)
|
||||
{
|
||||
return 0xc000;
|
||||
return (v & 0xff) << 24;
|
||||
}
|
||||
static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
|
||||
static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_128_v(void)
|
||||
{
|
||||
return (v & 0xff) << 18;
|
||||
return 0x00000080;
|
||||
}
|
||||
static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
|
||||
static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_disable_v(void)
|
||||
{
|
||||
return 0x2000000;
|
||||
return 0x00000000;
|
||||
}
|
||||
static inline u32 ram_rl_entry_tsg_length_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 26;
|
||||
return (v & 0xff) << 0;
|
||||
}
|
||||
static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_init_v(void)
|
||||
{
|
||||
return 0x00000000;
|
||||
}
|
||||
static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_min_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
}
|
||||
static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_max_v(void)
|
||||
{
|
||||
return 0x00000080;
|
||||
}
|
||||
static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v)
|
||||
{
|
||||
return (v & 0xfff) << 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -50,360 +50,4 @@
|
||||
#ifndef _hw_therm_gv11b_h_
|
||||
#define _hw_therm_gv11b_h_
|
||||
|
||||
static inline u32 therm_use_a_r(void)
|
||||
{
|
||||
return 0x00020798;
|
||||
}
|
||||
static inline u32 therm_use_a_ext_therm_0_enable_f(void)
|
||||
{
|
||||
return 0x1;
|
||||
}
|
||||
static inline u32 therm_use_a_ext_therm_1_enable_f(void)
|
||||
{
|
||||
return 0x2;
|
||||
}
|
||||
static inline u32 therm_use_a_ext_therm_2_enable_f(void)
|
||||
{
|
||||
return 0x4;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_0_r(void)
|
||||
{
|
||||
return 0x00020700;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 24;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_0_mode_f(u32 v)
|
||||
{
|
||||
return (v & 0x3) << 30;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_0_mode_normal_v(void)
|
||||
{
|
||||
return 0x00000000;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_0_mode_forced_v(void)
|
||||
{
|
||||
return 0x00000002;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void)
|
||||
{
|
||||
return 0x00000003;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_1_r(void)
|
||||
{
|
||||
return 0x00020704;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 24;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
|
||||
{
|
||||
return 0x00000002;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_1_mode_f(u32 v)
|
||||
{
|
||||
return (v & 0x3) << 30;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_1_mode_normal_v(void)
|
||||
{
|
||||
return 0x00000000;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_1_mode_forced_v(void)
|
||||
{
|
||||
return 0x00000002;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void)
|
||||
{
|
||||
return 0x00000003;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_2_r(void)
|
||||
{
|
||||
return 0x00020708;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 24;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
|
||||
{
|
||||
return 0x00000003;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_2_mode_f(u32 v)
|
||||
{
|
||||
return (v & 0x3) << 30;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_2_mode_normal_v(void)
|
||||
{
|
||||
return 0x00000000;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void)
|
||||
{
|
||||
return 0x00000001;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_2_mode_forced_v(void)
|
||||
{
|
||||
return 0x00000002;
|
||||
}
|
||||
static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void)
|
||||
{
|
||||
return 0x00000003;
|
||||
}
|
||||
static inline u32 therm_weight_1_r(void)
|
||||
{
|
||||
return 0x00020024;
|
||||
}
|
||||
static inline u32 therm_config1_r(void)
|
||||
{
|
||||
return 0x00020050;
|
||||
}
|
||||
static inline u32 therm_config2_r(void)
|
||||
{
|
||||
return 0x00020130;
|
||||
}
|
||||
static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
|
||||
{
|
||||
return (v & 0x1) << 24;
|
||||
}
|
||||
static inline u32 therm_config2_grad_enable_f(u32 v)
|
||||
{
|
||||
return (v & 0x1) << 31;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_r(u32 i)
|
||||
{
|
||||
return 0x00020200 + i*4;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_clk_m(void)
|
||||
{
|
||||
return 0x3 << 0;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
|
||||
{
|
||||
return 0x0;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
|
||||
{
|
||||
return 0x1;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
|
||||
{
|
||||
return 0x2;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_blk_clk_m(void)
|
||||
{
|
||||
return 0x3 << 2;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
|
||||
{
|
||||
return 0x0;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
|
||||
{
|
||||
return 0x4;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_pwr_m(void)
|
||||
{
|
||||
return 0x3 << 4;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
|
||||
{
|
||||
return 0x10;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
|
||||
{
|
||||
return 0x00000002;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
|
||||
{
|
||||
return 0x20;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
|
||||
{
|
||||
return (v & 0x1f) << 8;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
|
||||
{
|
||||
return 0x1f << 8;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
|
||||
{
|
||||
return (v & 0x7) << 13;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
|
||||
{
|
||||
return 0x7 << 13;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
|
||||
{
|
||||
return (v & 0xf) << 16;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
|
||||
{
|
||||
return 0xf << 16;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
|
||||
{
|
||||
return (v & 0xf) << 20;
|
||||
}
|
||||
static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
|
||||
{
|
||||
return 0xf << 20;
|
||||
}
|
||||
static inline u32 therm_fecs_idle_filter_r(void)
|
||||
{
|
||||
return 0x00020288;
|
||||
}
|
||||
static inline u32 therm_fecs_idle_filter_value_m(void)
|
||||
{
|
||||
return 0xffffffff << 0;
|
||||
}
|
||||
static inline u32 therm_hubmmu_idle_filter_r(void)
|
||||
{
|
||||
return 0x0002028c;
|
||||
}
|
||||
static inline u32 therm_hubmmu_idle_filter_value_m(void)
|
||||
{
|
||||
return 0xffffffff << 0;
|
||||
}
|
||||
static inline u32 therm_clk_slowdown_r(u32 i)
|
||||
{
|
||||
return 0x00020160 + i*4;
|
||||
}
|
||||
static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 16;
|
||||
}
|
||||
static inline u32 therm_clk_slowdown_idle_factor_m(void)
|
||||
{
|
||||
return 0x3f << 16;
|
||||
}
|
||||
static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
|
||||
{
|
||||
return (r >> 16) & 0x3f;
|
||||
}
|
||||
static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
|
||||
{
|
||||
return 0x0;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_r(u32 i)
|
||||
{
|
||||
return 0x000202c8 + i*4;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 0;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
|
||||
{
|
||||
return 0x3f << 0;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
|
||||
{
|
||||
return 0x1;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
|
||||
{
|
||||
return 0x2;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
|
||||
{
|
||||
return 0x6;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
|
||||
{
|
||||
return 0xe;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 6;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
|
||||
{
|
||||
return 0x3f << 6;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 12;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
|
||||
{
|
||||
return 0x3f << 12;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 18;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
|
||||
{
|
||||
return 0x3f << 18;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
|
||||
{
|
||||
return (v & 0x3f) << 24;
|
||||
}
|
||||
static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
|
||||
{
|
||||
return 0x3f << 24;
|
||||
}
|
||||
static inline u32 therm_grad_stepping0_r(void)
|
||||
{
|
||||
return 0x000202c0;
|
||||
}
|
||||
static inline u32 therm_grad_stepping0_feature_s(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
static inline u32 therm_grad_stepping0_feature_f(u32 v)
|
||||
{
|
||||
return (v & 0x1) << 0;
|
||||
}
|
||||
static inline u32 therm_grad_stepping0_feature_m(void)
|
||||
{
|
||||
return 0x1 << 0;
|
||||
}
|
||||
static inline u32 therm_grad_stepping0_feature_v(u32 r)
|
||||
{
|
||||
return (r >> 0) & 0x1;
|
||||
}
|
||||
static inline u32 therm_grad_stepping0_feature_enable_f(void)
|
||||
{
|
||||
return 0x1;
|
||||
}
|
||||
static inline u32 therm_grad_stepping1_r(void)
|
||||
{
|
||||
return 0x000202c4;
|
||||
}
|
||||
static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
|
||||
{
|
||||
return (v & 0x1ffff) << 0;
|
||||
}
|
||||
static inline u32 therm_clk_timing_r(u32 i)
|
||||
{
|
||||
return 0x000203c0 + i*4;
|
||||
}
|
||||
static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
|
||||
{
|
||||
return (v & 0x1) << 16;
|
||||
}
|
||||
static inline u32 therm_clk_timing_grad_slowdown_m(void)
|
||||
{
|
||||
return 0x1 << 16;
|
||||
}
|
||||
static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
|
||||
{
|
||||
return 0x10000;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -208,7 +208,7 @@ static inline u32 top_device_info_data_pri_base_align_v(void)
|
||||
}
|
||||
static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
|
||||
{
|
||||
return (r >> 3) & 0x1f;
|
||||
return (r >> 3) & 0x7f;
|
||||
}
|
||||
static inline u32 top_device_info_data_fault_id_v(u32 r)
|
||||
{
|
||||
|
||||
89
drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h
Normal file
89
drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h
Normal file
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
/*
|
||||
* Function naming determines intended use:
|
||||
*
|
||||
* <x>_r(void) : Returns the offset for register <x>.
|
||||
*
|
||||
* <x>_o(void) : Returns the offset for element <x>.
|
||||
*
|
||||
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
|
||||
*
|
||||
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
|
||||
*
|
||||
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
|
||||
* and masked to place it at field <y> of register <x>. This value
|
||||
* can be |'d with others to produce a full register value for
|
||||
* register <x>.
|
||||
*
|
||||
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
|
||||
* value can be ~'d and then &'d to clear the value of field <y> for
|
||||
* register <x>.
|
||||
*
|
||||
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
|
||||
* to place it at field <y> of register <x>. This value can be |'d
|
||||
* with others to produce a full register value for <x>.
|
||||
*
|
||||
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
|
||||
* <x> value 'r' after being shifted to place its LSB at bit 0.
|
||||
* This value is suitable for direct comparison with other unshifted
|
||||
* values appropriate for use in field <y> of register <x>.
|
||||
*
|
||||
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
|
||||
* field <y> of register <x>. This value is suitable for direct
|
||||
* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
#ifndef _hw_usermode_gv11b_h_
|
||||
#define _hw_usermode_gv11b_h_
|
||||
|
||||
static inline u32 usermode_cfg0_r(void)
|
||||
{
|
||||
return 0x00810000;
|
||||
}
|
||||
static inline u32 usermode_cfg0_usermode_class_id_f(u32 v)
|
||||
{
|
||||
return (v & 0xffff) << 0;
|
||||
}
|
||||
static inline u32 usermode_cfg0_usermode_class_id_value_v(void)
|
||||
{
|
||||
return 0x0000c361;
|
||||
}
|
||||
static inline u32 usermode_time_0_r(void)
|
||||
{
|
||||
return 0x00810080;
|
||||
}
|
||||
static inline u32 usermode_time_0_nsec_f(u32 v)
|
||||
{
|
||||
return (v & 0x7ffffff) << 5;
|
||||
}
|
||||
static inline u32 usermode_time_1_r(void)
|
||||
{
|
||||
return 0x00810084;
|
||||
}
|
||||
static inline u32 usermode_time_1_nsec_f(u32 v)
|
||||
{
|
||||
return (v & 0x1fffffff) << 0;
|
||||
}
|
||||
static inline u32 usermode_notify_channel_pending_r(void)
|
||||
{
|
||||
return 0x00810090;
|
||||
}
|
||||
static inline u32 usermode_notify_channel_pending_id_f(u32 v)
|
||||
{
|
||||
return (v & 0xffffffff) << 0;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user