diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index e413e5784..4ca2d82c8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_CCSR_GV11B_H #define NVGPU_HW_CCSR_GV11B_H +#include + static inline u32 ccsr_channel_inst_r(u32 i) { return 0x00800000U + i*8U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index e06ce8ab3..9c53609e2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_CE_GV11B_H #define NVGPU_HW_CE_GV11B_H +#include + static inline u32 ce_intr_status_r(u32 i) { return 0x00104410U + i*128U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index 5a9578b84..9f2ae2db5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_CTXSW_PROG_GV11B_H #define NVGPU_HW_CTXSW_PROG_GV11B_H +#include + static inline u32 ctxsw_prog_fecs_header_v(void) { return 0x00000100U; @@ -138,7 +140,7 @@ static inline u32 ctxsw_prog_main_image_pm_o(void) } static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { - return 0x7U << 0U; + return U32(0x7U) << 0U; } static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { @@ -150,7 +152,7 @@ static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void) } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) { - return 0x7U << 3U; + return U32(0x7U) << 3U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) { @@ -394,7 +396,7 @@ static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) { - return 0x3U << 0U; + return U32(0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) { @@ -422,7 +424,7 @@ static inline u32 ctxsw_prog_main_image_misc_options_o(void) } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index d0f6b83e0..fbc277868 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_FALCON_GV11B_H #define NVGPU_HW_FALCON_GV11B_H +#include + static inline u32 falcon_falcon_irqsset_r(void) { return 0x00000000U; @@ -310,7 +312,7 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) } static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) { @@ -318,7 +320,7 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) } static inline u32 falcon_falcon_cpuctl_stopped_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) { @@ -326,7 +328,7 @@ static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) } static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) { @@ -390,11 +392,11 @@ static inline u32 falcon_falcon_dmactl_r(void) } static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) { @@ -494,7 +496,7 @@ static inline u32 falcon_falcon_exterrstat_r(void) } static inline u32 falcon_falcon_exterrstat_valid_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) { @@ -518,7 +520,7 @@ static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) } static inline u32 falcon_falcon_icd_cmd_opc_m(void) { - return 0xfU << 0U; + return U32(0xfU) << 0U; } static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) { @@ -550,7 +552,7 @@ static inline u32 falcon_falcon_dmemc_offs_f(u32 v) } static inline u32 falcon_falcon_dmemc_offs_m(void) { - return 0x3fU << 2U; + return U32(0x3fU) << 2U; } static inline u32 falcon_falcon_dmemc_blk_f(u32 v) { @@ -558,7 +560,7 @@ static inline u32 falcon_falcon_dmemc_blk_f(u32 v) } static inline u32 falcon_falcon_dmemc_blk_m(void) { - return 0xffU << 8U; + return U32(0xffU) << 8U; } static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) { @@ -586,7 +588,7 @@ static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) } static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 360b23f24..6c451f04a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_FB_GV11B_H #define NVGPU_HW_FB_GV11B_H +#include + static inline u32 fb_fbhub_num_active_ltcs_r(void) { return 0x00100800U; @@ -118,7 +120,7 @@ static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) } static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) { @@ -138,7 +140,7 @@ static inline u32 fb_mmu_invalidate_replay_f(u32 v) } static inline u32 fb_mmu_invalidate_replay_m(void) { - return 0x7U << 3U; + return U32(0x7U) << 3U; } static inline u32 fb_mmu_invalidate_replay_v(u32 r) { @@ -170,7 +172,7 @@ static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) } static inline u32 fb_mmu_invalidate_sys_membar_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) { @@ -190,7 +192,7 @@ static inline u32 fb_mmu_invalidate_ack_f(u32 v) } static inline u32 fb_mmu_invalidate_ack_m(void) { - return 0x3U << 7U; + return U32(0x3U) << 7U; } static inline u32 fb_mmu_invalidate_ack_v(u32 r) { @@ -218,7 +220,7 @@ static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) } static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) { - return 0x3fU << 9U; + return U32(0x3fU) << 9U; } static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) { @@ -234,7 +236,7 @@ static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) } static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) { - return 0x1fU << 15U; + return U32(0x1fU) << 15U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) { @@ -250,7 +252,7 @@ static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) } static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) { - return 0x1U << 20U; + return U32(0x1U) << 20U; } static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) { @@ -274,7 +276,7 @@ static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) } static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) { - return 0x7U << 24U; + return U32(0x7U) << 24U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) { @@ -322,7 +324,7 @@ static inline u32 fb_mmu_invalidate_trigger_f(u32 v) } static inline u32 fb_mmu_invalidate_trigger_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 fb_mmu_invalidate_trigger_v(u32 r) { @@ -346,7 +348,7 @@ static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) } static inline u32 fb_mmu_debug_wr_aperture_m(void) { - return 0x3U << 0U; + return U32(0x3U) << 0U; } static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) { @@ -422,7 +424,7 @@ static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) } static inline u32 fb_mmu_debug_ctrl_debug_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) { @@ -454,19 +456,19 @@ static inline u32 fb_mmu_l2tlb_ecc_status_r(void) } static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1U << 18U; + return U32(0x1U) << 18U; } static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) { @@ -490,7 +492,7 @@ static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) { @@ -510,7 +512,7 @@ static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) { @@ -530,7 +532,7 @@ static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) } static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) { - return 0xffffffffU << 0U; + return U32(0xffffffffU) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) { @@ -542,19 +544,19 @@ static inline u32 fb_mmu_hubtlb_ecc_status_r(void) } static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1U << 18U; + return U32(0x1U) << 18U; } static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) { @@ -578,7 +580,7 @@ static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) { @@ -598,7 +600,7 @@ static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) { @@ -618,7 +620,7 @@ static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) } static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) { - return 0xffffffffU << 0U; + return U32(0xffffffffU) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) { @@ -630,27 +632,27 @@ static inline u32 fb_mmu_fillunit_ecc_status_r(void) } static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1U << 18U; + return U32(0x1U) << 18U; } static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) { @@ -674,7 +676,7 @@ static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) { @@ -694,7 +696,7 @@ static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) { @@ -714,7 +716,7 @@ static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) } static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) { - return 0xffffffffU << 0U; + return U32(0xffffffffU) << 0U; } static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) { @@ -730,7 +732,7 @@ static inline u32 fb_niso_intr_r(void) } static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) { @@ -738,7 +740,7 @@ static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) } static inline u32 fb_niso_intr_hub_access_counter_error_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) { @@ -746,7 +748,7 @@ static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) { - return 0x1U << 27U; + return U32(0x1U) << 27U; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) { @@ -754,7 +756,7 @@ static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) { - return 0x1U << 28U; + return U32(0x1U) << 28U; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) { @@ -762,7 +764,7 @@ static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1U << 29U; + return U32(0x1U) << 29U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) { @@ -770,7 +772,7 @@ static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) { @@ -778,7 +780,7 @@ static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) } static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) { @@ -786,7 +788,7 @@ static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) } static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void) { - return 0x1U << 26U; + return U32(0x1U) << 26U; } static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) { @@ -874,7 +876,7 @@ static inline u32 fb_niso_intr_en_set__size_1_v(void) } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) { @@ -882,7 +884,7 @@ static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) { @@ -890,7 +892,7 @@ static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) { - return 0x1U << 27U; + return U32(0x1U) << 27U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) { @@ -898,7 +900,7 @@ static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) { - return 0x1U << 28U; + return U32(0x1U) << 28U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) { @@ -906,7 +908,7 @@ static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) { - return 0x1U << 29U; + return U32(0x1U) << 29U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) { @@ -914,7 +916,7 @@ static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) { @@ -922,7 +924,7 @@ static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(voi } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) { @@ -930,7 +932,7 @@ static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) } static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void) { - return 0x1U << 26U; + return U32(0x1U) << 26U; } static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) { @@ -946,7 +948,7 @@ static inline u32 fb_niso_intr_en_clr__size_1_v(void) } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) { @@ -954,7 +956,7 @@ static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) { @@ -962,7 +964,7 @@ static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) { - return 0x1U << 27U; + return U32(0x1U) << 27U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) { @@ -970,7 +972,7 @@ static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) { - return 0x1U << 28U; + return U32(0x1U) << 28U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) { @@ -978,7 +980,7 @@ static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1U << 29U; + return U32(0x1U) << 29U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) { @@ -986,7 +988,7 @@ static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) { @@ -994,7 +996,7 @@ static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(voi } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) { @@ -1002,7 +1004,7 @@ static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) } static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void) { - return 0x1U << 26U; + return U32(0x1U) << 26U; } static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) { @@ -1122,7 +1124,7 @@ static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) } static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) { - return 0xfffffU << 0U; + return U32(0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) { @@ -1134,7 +1136,7 @@ static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) { @@ -1150,7 +1152,7 @@ static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) } static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) { @@ -1270,7 +1272,7 @@ static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) } static inline u32 fb_mmu_fault_buffer_size_enable_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) { @@ -1422,7 +1424,7 @@ static inline u32 fb_mmu_fault_status_r(void) } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) { @@ -1442,7 +1444,7 @@ static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) { @@ -1462,7 +1464,7 @@ static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) { @@ -1482,7 +1484,7 @@ static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) { @@ -1502,7 +1504,7 @@ static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) { @@ -1522,7 +1524,7 @@ static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) { @@ -1542,7 +1544,7 @@ static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) } static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) { @@ -1562,7 +1564,7 @@ static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) } static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) { - return 0x1U << 7U; + return U32(0x1U) << 7U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) { @@ -1582,7 +1584,7 @@ static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) } static inline u32 fb_mmu_fault_status_replayable_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 fb_mmu_fault_status_replayable_set_v(void) { @@ -1598,7 +1600,7 @@ static inline u32 fb_mmu_fault_status_replayable_reset_f(void) } static inline u32 fb_mmu_fault_status_non_replayable_m(void) { - return 0x1U << 9U; + return U32(0x1U) << 9U; } static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) { @@ -1614,7 +1616,7 @@ static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) } static inline u32 fb_mmu_fault_status_replayable_error_m(void) { - return 0x1U << 10U; + return U32(0x1U) << 10U; } static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) { @@ -1630,7 +1632,7 @@ static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) } static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) { - return 0x1U << 11U; + return U32(0x1U) << 11U; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) { @@ -1646,7 +1648,7 @@ static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) } static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) { - return 0x1U << 12U; + return U32(0x1U) << 12U; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) { @@ -1662,7 +1664,7 @@ static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) } static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) { - return 0x1U << 13U; + return U32(0x1U) << 13U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) { @@ -1678,7 +1680,7 @@ static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) { - return 0x1U << 14U; + return U32(0x1U) << 14U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) { @@ -1690,7 +1692,7 @@ static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) { - return 0x1U << 15U; + return U32(0x1U) << 15U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) { @@ -1702,7 +1704,7 @@ static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void } static inline u32 fb_mmu_fault_status_busy_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 fb_mmu_fault_status_busy_true_v(void) { @@ -1714,7 +1716,7 @@ static inline u32 fb_mmu_fault_status_busy_true_f(void) } static inline u32 fb_mmu_fault_status_valid_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 fb_mmu_fault_status_valid_set_v(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index 0904a59e9..5d28628ea 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_FIFO_GV11B_H #define NVGPU_HW_FIFO_GV11B_H +#include + static inline u32 fifo_userd_writeback_r(void) { return 0x0000225cU; @@ -230,7 +232,7 @@ static inline u32 fifo_intr_en_0_sched_error_f(u32 v) } static inline u32 fifo_intr_en_0_sched_error_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) { @@ -358,7 +360,7 @@ static inline u32 fifo_fb_timeout_r(void) } static inline u32 fifo_fb_timeout_period_m(void) { - return 0x3fffffffU << 0U; + return U32(0x3fffffffU) << 0U; } static inline u32 fifo_fb_timeout_period_max_f(void) { @@ -370,7 +372,7 @@ static inline u32 fifo_fb_timeout_period_init_f(void) } static inline u32 fifo_fb_timeout_detection_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 fifo_fb_timeout_detection_enabled_f(void) { @@ -390,7 +392,7 @@ static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) } static inline u32 fifo_sched_disable_runlist_m(u32 i) { - return 0x1U << (0U + i*1U); + return U32(0x1U) << (0U + i*1U); } static inline u32 fifo_sched_disable_true_v(void) { @@ -406,7 +408,7 @@ static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) } static inline u32 fifo_runlist_preempt_runlist_m(u32 i) { - return 0x1U << (0U + i*1U); + return U32(0x1U) << (0U + i*1U); } static inline u32 fifo_runlist_preempt_runlist_pending_v(void) { @@ -542,7 +544,7 @@ static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) } static inline u32 fifo_eng_ctxsw_timeout_period_m(void) { - return 0x7fffffffU << 0U; + return U32(0x7fffffffU) << 0U; } static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) { @@ -562,7 +564,7 @@ static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) } static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h index 053099fbd..1aa6a6263 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_FLUSH_GV11B_H #define NVGPU_HW_FLUSH_GV11B_H +#include + static inline u32 flush_l2_system_invalidate_r(void) { return 0x00070004U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h index fa080ca3c..bf6048635 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_FUSE_GV11B_H #define NVGPU_HW_FUSE_GV11B_H +#include + static inline u32 fuse_status_opt_gpc_r(void) { return 0x00021c1cU; @@ -78,7 +80,7 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) { - return 0xffU << 0U; + return U32(0xffU) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) { @@ -94,7 +96,7 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) { @@ -118,7 +120,7 @@ static inline u32 fuse_status_opt_fbio_data_f(u32 v) } static inline u32 fuse_status_opt_fbio_data_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 fuse_status_opt_fbio_data_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index 67a065eed..a00c520c8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_GMMU_GV11B_H #define NVGPU_HW_GMMU_GV11B_H +#include + static inline u32 gmmu_new_pde_is_pte_w(void) { return 0U; @@ -550,7 +552,7 @@ static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) } static inline u32 gmmu_fault_buf_entry_valid_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 404c7e54c..b111ce63a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_GR_GV11B_H #define NVGPU_HW_GR_GV11B_H +#include + static inline u32 gr_intr_r(void) { return 0x00400100U; @@ -166,39 +168,39 @@ static inline u32 gr_exception_r(void) } static inline u32 gr_exception_fe_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_exception_gpc_m(void) { - return 0x1U << 24U; + return U32(0x1U) << 24U; } static inline u32 gr_exception_memfmt_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_exception_ds_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_exception_sked_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 gr_exception_pd_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_exception_scc_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 gr_exception_ssync_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_exception_mme_m(void) { - return 0x1U << 7U; + return U32(0x1U) << 7U; } static inline u32 gr_exception1_r(void) { @@ -218,7 +220,7 @@ static inline u32 gr_exception_en_r(void) } static inline u32 gr_exception_en_fe_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_exception_en_fe_enabled_f(void) { @@ -226,7 +228,7 @@ static inline u32 gr_exception_en_fe_enabled_f(void) } static inline u32 gr_exception_en_gpc_m(void) { - return 0x1U << 24U; + return U32(0x1U) << 24U; } static inline u32 gr_exception_en_gpc_enabled_f(void) { @@ -234,7 +236,7 @@ static inline u32 gr_exception_en_gpc_enabled_f(void) } static inline u32 gr_exception_en_memfmt_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_exception_en_memfmt_enabled_f(void) { @@ -242,7 +244,7 @@ static inline u32 gr_exception_en_memfmt_enabled_f(void) } static inline u32 gr_exception_en_ds_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_exception_en_ds_enabled_f(void) { @@ -250,7 +252,7 @@ static inline u32 gr_exception_en_ds_enabled_f(void) } static inline u32 gr_exception_en_pd_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_exception_en_pd_enabled_f(void) { @@ -258,7 +260,7 @@ static inline u32 gr_exception_en_pd_enabled_f(void) } static inline u32 gr_exception_en_scc_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 gr_exception_en_scc_enabled_f(void) { @@ -266,7 +268,7 @@ static inline u32 gr_exception_en_scc_enabled_f(void) } static inline u32 gr_exception_en_ssync_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_exception_en_ssync_enabled_f(void) { @@ -274,7 +276,7 @@ static inline u32 gr_exception_en_ssync_enabled_f(void) } static inline u32 gr_exception_en_mme_m(void) { - return 0x1U << 7U; + return U32(0x1U) << 7U; } static inline u32 gr_exception_en_mme_enabled_f(void) { @@ -282,7 +284,7 @@ static inline u32 gr_exception_en_mme_enabled_f(void) } static inline u32 gr_exception_en_sked_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 gr_exception_en_sked_enabled_f(void) { @@ -462,7 +464,7 @@ static inline u32 gr_activity_4_gpc0_f(u32 v) } static inline u32 gr_activity_4_gpc0_m(void) { - return 0x7U << 0U; + return U32(0x7U) << 0U; } static inline u32 gr_activity_4_gpc0_v(u32 r) { @@ -486,7 +488,7 @@ static inline u32 gr_pri_gpcs_gcc_dbg_r(void) } static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) { @@ -498,7 +500,7 @@ static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_pri_sked_activity_r(void) { @@ -602,67 +604,67 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) { - return 0x1U << 7U; + return U32(0x1U) << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) { - return 0x1U << 9U; + return U32(0x1U) << 9U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) { - return 0x1U << 10U; + return U32(0x1U) << 10U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) { - return 0x1U << 11U; + return U32(0x1U) << 11U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) { - return 0x1U << 12U; + return U32(0x1U) << 12U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) { - return 0x1U << 13U; + return U32(0x1U) << 13U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) { - return 0x1U << 14U; + return U32(0x1U) << 14U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) { - return 0x1U << 15U; + return U32(0x1U) << 15U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { @@ -706,19 +708,19 @@ static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { @@ -762,35 +764,35 @@ static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) { - return 0x1U << 7U; + return U32(0x1U) << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { @@ -834,35 +836,35 @@ static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void) { - return 0x1U << 7U; + return U32(0x1U) << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { @@ -906,35 +908,35 @@ static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) { - return 0x1U << 7U; + return U32(0x1U) << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { @@ -1506,7 +1508,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) { @@ -1514,7 +1516,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) { @@ -1522,7 +1524,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) { @@ -1530,7 +1532,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) { @@ -1538,7 +1540,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) { @@ -1586,7 +1588,7 @@ static inline u32 gr_fe_tpc_pesmask_gpcid_f(u32 v) } static inline u32 gr_fe_tpc_pesmask_action_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 gr_fe_tpc_pesmask_action_write_f(void) { @@ -1598,7 +1600,7 @@ static inline u32 gr_fe_tpc_pesmask_action_read_f(void) } static inline u32 gr_fe_tpc_pesmask_req_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 gr_fe_tpc_pesmask_req_send_f(void) { @@ -1606,7 +1608,7 @@ static inline u32 gr_fe_tpc_pesmask_req_send_f(void) } static inline u32 gr_fe_tpc_pesmask_mask_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 gr_pri_mme_shadow_raw_index_r(void) { @@ -1674,11 +1676,11 @@ static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) } static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_fecs_os_r(void) { @@ -1746,7 +1748,7 @@ static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) } static inline u32 gr_fecs_icd_cmd_opc_m(void) { - return 0xfU << 0U; + return U32(0xfU) << 0U; } static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) { @@ -1810,7 +1812,7 @@ static inline u32 gr_fecs_dmemc_offs_f(u32 v) } static inline u32 gr_fecs_dmemc_offs_m(void) { - return 0x3fU << 2U; + return U32(0x3fU) << 2U; } static inline u32 gr_fecs_dmemc_offs_v(u32 r) { @@ -1902,7 +1904,7 @@ static inline u32 gr_fecs_current_ctx_target_f(u32 v) } static inline u32 gr_fecs_current_ctx_target_m(void) { - return 0x3U << 28U; + return U32(0x3U) << 28U; } static inline u32 gr_fecs_current_ctx_target_v(u32 r) { @@ -1930,7 +1932,7 @@ static inline u32 gr_fecs_current_ctx_valid_f(u32 v) } static inline u32 gr_fecs_current_ctx_valid_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 gr_fecs_current_ctx_valid_v(u32 r) { @@ -2046,7 +2048,7 @@ static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) } static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) { - return 0x1U << 21U; + return U32(0x1U) << 21U; } static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) { @@ -2054,7 +2056,7 @@ static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) } static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) { - return 0x1U << 22U; + return U32(0x1U) << 22U; } static inline u32 gr_fecs_host_int_clear_r(void) { @@ -2158,7 +2160,7 @@ static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) { - return 0x1U << 10U; + return U32(0x1U) << 10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) { @@ -2226,7 +2228,7 @@ static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) } static inline u32 gr_fecs_fs_num_available_gpcs_m(void) { - return 0x1fU << 0U; + return U32(0x1fU) << 0U; } static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) { @@ -2242,7 +2244,7 @@ static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) } static inline u32 gr_fecs_fs_num_available_fbps_m(void) { - return 0x1fU << 16U; + return U32(0x1fU) << 16U; } static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) { @@ -2270,7 +2272,7 @@ static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) } static inline u32 gr_fecs_rc_lanes_num_chains_m(void) { - return 0x3fU << 0U; + return U32(0x3fU) << 0U; } static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) { @@ -2290,7 +2292,7 @@ static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) { - return 0x1U << 12U; + return U32(0x1U) << 12U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) { @@ -2314,7 +2316,7 @@ static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) } static inline u32 gr_fecs_new_ctx_ptr_m(void) { - return 0xfffffffU << 0U; + return U32(0xfffffffU) << 0U; } static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) { @@ -2330,7 +2332,7 @@ static inline u32 gr_fecs_new_ctx_target_f(u32 v) } static inline u32 gr_fecs_new_ctx_target_m(void) { - return 0x3U << 28U; + return U32(0x3U) << 28U; } static inline u32 gr_fecs_new_ctx_target_v(u32 r) { @@ -2346,7 +2348,7 @@ static inline u32 gr_fecs_new_ctx_valid_f(u32 v) } static inline u32 gr_fecs_new_ctx_valid_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 gr_fecs_new_ctx_valid_v(u32 r) { @@ -2366,7 +2368,7 @@ static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) } static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) { - return 0xfffffffU << 0U; + return U32(0xfffffffU) << 0U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) { @@ -2382,7 +2384,7 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) } static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) { - return 0x3U << 28U; + return U32(0x3U) << 28U; } static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) { @@ -2402,7 +2404,7 @@ static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) } static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) { - return 0x1fU << 0U; + return U32(0x1fU) << 0U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) { @@ -2722,7 +2724,7 @@ static inline u32 gr_ds_zbc_z_val_f(u32 v) } static inline u32 gr_ds_zbc_z_val_m(void) { - return 0xffffffffU << 0U; + return U32(0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_z_val_v(u32 r) { @@ -2810,7 +2812,7 @@ static inline u32 gr_ds_hww_esr_reset_f(u32 v) } static inline u32 gr_ds_hww_esr_reset_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 gr_ds_hww_esr_reset_v(u32 r) { @@ -2842,7 +2844,7 @@ static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) } static inline u32 gr_ds_hww_esr_2_reset_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) { @@ -2978,7 +2980,7 @@ static inline u32 gr_scc_debug_r(void) } static inline u32 gr_scc_debug_pagepool_invalidates_m(void) { - return 0x1U << 9U; + return U32(0x1U) << 9U; } static inline u32 gr_scc_debug_pagepool_invalidates_disable_f(void) { @@ -3070,7 +3072,7 @@ static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) } static inline u32 gr_scc_pagepool_max_valid_pages_m(void) { - return 0x3ffU << 10U; + return U32(0x3ffU) << 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) { @@ -3126,7 +3128,7 @@ static inline u32 gr_sked_hww_esr_en_r(void) } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) { - return 0x1U << 25U; + return U32(0x1U) << 25U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) { @@ -3222,7 +3224,7 @@ static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) } static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) { - return 0x3fU << 0U; + return U32(0x3fU) << 0U; } static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) { @@ -3242,7 +3244,7 @@ static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) } static inline u32 gr_gpccs_rc_lane_size_v_m(void) { - return 0xffffffU << 0U; + return U32(0xffffffU) << 0U; } static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) { @@ -3370,7 +3372,7 @@ static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) { @@ -3386,7 +3388,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) { - return 0x3fffffU << 0U; + return U32(0x3fffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { @@ -3414,7 +3416,7 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) { @@ -3462,7 +3464,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) { - return 0x1fffffU << 0U; + return U32(0x1fffffU) << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) { @@ -3482,7 +3484,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) { @@ -3506,7 +3508,7 @@ static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) } static inline u32 gr_gpccs_falcon_addr_lsb_m(void) { - return 0x3fU << 0U; + return U32(0x3fU) << 0U; } static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) { @@ -3530,7 +3532,7 @@ static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) } static inline u32 gr_gpccs_falcon_addr_msb_m(void) { - return 0x3fU << 6U; + return U32(0x3fU) << 6U; } static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) { @@ -3554,7 +3556,7 @@ static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) } static inline u32 gr_gpccs_falcon_addr_ext_m(void) { - return 0xfffU << 0U; + return U32(0xfffU) << 0U; } static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) { @@ -3578,11 +3580,11 @@ static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) } static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_gpccs_imemc_r(u32 i) { @@ -3658,7 +3660,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) { - return 0xffffffffU << 0U; + return U32(0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) { @@ -3686,7 +3688,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) { - return 0x7ffU << 0U; + return U32(0x7ffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) { @@ -3710,7 +3712,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) { @@ -3786,7 +3788,7 @@ static inline u32 gr_gpcs_ppcs_cbm_debug_r(void) } static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_disable_f(void) { @@ -3798,7 +3800,7 @@ static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_enable_f(void) } static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f(void) { @@ -3818,7 +3820,7 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { - return 0x3fffffU << 0U; + return U32(0x3fffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) { @@ -3886,7 +3888,7 @@ static inline u32 gr_gpcs_swdx_spill_unit_r(void) } static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_disabled_f(void) { @@ -4206,7 +4208,7 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) } static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) { - return 0x1U << 14U; + return U32(0x1U) << 14U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) { @@ -4218,7 +4220,7 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v) } static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void) { - return 0x1U << 15U; + return U32(0x1U) << 15U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void) { @@ -4230,19 +4232,19 @@ static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { @@ -4302,7 +4304,7 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) { @@ -4314,7 +4316,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) { @@ -4338,7 +4340,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) { @@ -4350,7 +4352,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) { @@ -4506,11 +4508,11 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void) } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) { - return 0xffU << 16U; + return U32(0xffU) << 16U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) { - return 0xfU << 24U; + return U32(0xfU) << 24U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) { @@ -4546,7 +4548,7 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) { @@ -4562,7 +4564,7 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) { @@ -4650,11 +4652,11 @@ static inline u32 gr_bes_crop_debug3_r(void) } static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) { @@ -4666,7 +4668,7 @@ static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) { @@ -4682,7 +4684,7 @@ static inline u32 gr_bes_crop_debug4_r(void) } static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) { - return 0x1U << 18U; + return U32(0x1U) << 18U; } static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) { @@ -4726,7 +4728,7 @@ static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) } static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) { - return 0x1U << 19U; + return U32(0x1U) << 19U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) { @@ -4738,7 +4740,7 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) { @@ -4746,11 +4748,11 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) { - return 0x1U << 10U; + return U32(0x1U) << 10U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void) { - return 0x1U << 28U; + return U32(0x1U) << 28U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void) { @@ -4942,39 +4944,39 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) } static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) { - return 0x1U << 11U; + return U32(0x1U) << 11U; } static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) { - return 0x3U << 3U; + return U32(0x3U) << 3U; } static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) { - return 0x3U << 5U; + return U32(0x3U) << 5U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) { - return 0x3U << 28U; + return U32(0x3U) << 28U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) { @@ -5038,7 +5040,7 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) { - return 0x7U << 8U; + return U32(0x7U) << 8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) { @@ -5050,7 +5052,7 @@ static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) { - return 0x3U << 11U; + return U32(0x3U) << 11U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) { @@ -5066,7 +5068,7 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { - return 0x1ffU << 0U; + return U32(0x1ffU) << 0U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void) { @@ -5078,7 +5080,7 @@ static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v) } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) { @@ -5086,7 +5088,7 @@ static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void) { @@ -5098,7 +5100,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v) { @@ -5106,7 +5108,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v) { @@ -5114,7 +5116,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v) { @@ -5122,7 +5124,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { @@ -5130,7 +5132,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_ove } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1U << 18U; + return U32(0x1U) << 18U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { @@ -5138,7 +5140,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overf } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { @@ -5146,7 +5148,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_ov } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1U << 19U; + return U32(0x1U) << 19U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { @@ -5154,7 +5156,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_over } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1U << 17U; + return U32(0x1U) << 17U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v) { @@ -5186,7 +5188,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v) } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r) { @@ -5202,7 +5204,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r) { @@ -5222,7 +5224,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v) } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r) { @@ -5238,7 +5240,7 @@ static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r) { @@ -5254,7 +5256,7 @@ static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) { @@ -5266,7 +5268,7 @@ static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) { @@ -5282,7 +5284,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) { @@ -5294,7 +5296,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) { @@ -5306,7 +5308,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) { @@ -5318,7 +5320,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) { @@ -5330,7 +5332,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_ } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1U << 10U; + return U32(0x1U) << 10U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) { @@ -5342,7 +5344,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_ov } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) { @@ -5354,7 +5356,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1U << 11U; + return U32(0x1U) << 11U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) { @@ -5366,7 +5368,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_o } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1U << 9U; + return U32(0x1U) << 9U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) { @@ -5398,7 +5400,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) { - return 0xfffffU << 0U; + return U32(0xfffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) { @@ -5418,7 +5420,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) { @@ -5434,7 +5436,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u3 } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) { @@ -5450,7 +5452,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) { @@ -5466,7 +5468,7 @@ static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f( } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { @@ -5482,7 +5484,7 @@ static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) { @@ -5494,7 +5496,7 @@ static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) { @@ -5506,7 +5508,7 @@ static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) { @@ -5518,7 +5520,7 @@ static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) { @@ -5530,7 +5532,7 @@ static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overfl } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1U << 10U; + return U32(0x1U) << 10U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) { @@ -5542,7 +5544,7 @@ static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) { @@ -5554,7 +5556,7 @@ static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overf } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1U << 11U; + return U32(0x1U) << 11U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) { @@ -5566,7 +5568,7 @@ static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflo } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1U << 9U; + return U32(0x1U) << 9U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) { @@ -5598,7 +5600,7 @@ static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) } static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) { - return 0xfffffU << 0U; + return U32(0xfffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) { @@ -5618,7 +5620,7 @@ static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) { @@ -5634,7 +5636,7 @@ static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) { @@ -5650,7 +5652,7 @@ static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) { @@ -5666,7 +5668,7 @@ static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { @@ -5678,7 +5680,7 @@ static inline u32 gr_debug_0_r(void) } static inline u32 gr_debug_0_scg_force_slow_drain_tpc_m(void) { - return 0x1U << 11U; + return U32(0x1U) << 11U; } static inline u32 gr_debug_0_scg_force_slow_drain_tpc_enabled_f(void) { @@ -5694,7 +5696,7 @@ static inline u32 gr_debug_2_r(void) } static inline u32 gr_debug_2_gfxp_wfi_timeout_unit_m(void) { - return 0x1U << 27U; + return U32(0x1U) << 27U; } static inline u32 gr_debug_2_gfxp_wfi_timeout_unit_usec_f(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index eb74894fb..ad927c714 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_LTC_GV11B_H #define NVGPU_HW_LTC_GV11B_H +#include + static inline u32 ltc_pltcg_base_v(void) { return 0x00140000U; @@ -90,7 +92,7 @@ static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) } static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) { - return 0x1U << 15U; + return U32(0x1U) << 15U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) { @@ -266,7 +268,7 @@ static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) { - return 0xffffffffU << 0U; + return U32(0xffffffffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) { @@ -286,7 +288,7 @@ static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) { - return 0xffU << 0U; + return U32(0xffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) { @@ -362,11 +364,11 @@ static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) } static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) { - return 0x1U << 20U; + return U32(0x1U) << 20U; } static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) { - return 0x1U << 21U; + return U32(0x1U) << 21U; } static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f(void) { @@ -378,7 +380,7 @@ static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f(void) } static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) { - return 0x1U << 30U; + return U32(0x1U) << 30U; } static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) { @@ -398,11 +400,11 @@ static inline u32 ltc_ltcs_ltss_intr3_r(void) } static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void) { - return 0x1U << 7U; + return U32(0x1U) << 7U; } static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 ltc_ltc0_lts0_intr3_r(void) { @@ -418,7 +420,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v) } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) { @@ -426,7 +428,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void) { - return 0x1U << 3U; + return U32(0x1U) << 3U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) { @@ -434,7 +436,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v) { @@ -442,7 +444,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v) { @@ -450,7 +452,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v) { @@ -458,7 +460,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { @@ -466,7 +468,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counte } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1U << 18U; + return U32(0x1U) << 18U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { @@ -474,7 +476,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_ } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { @@ -482,7 +484,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_count } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1U << 19U; + return U32(0x1U) << 19U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { @@ -490,7 +492,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1U << 17U; + return U32(0x1U) << 17U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v) { @@ -518,7 +520,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v) } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r) { @@ -534,7 +536,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f( } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r) { @@ -554,7 +556,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r) { @@ -570,7 +572,7 @@ static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_ } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r) { @@ -582,7 +584,7 @@ static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) { - return 0xffU << 0U; + return U32(0xffU) << 0U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) { @@ -590,7 +592,7 @@ static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) { - return 0xffU << 16U; + return U32(0xffU) << 16U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index bcdf08f70..16adc487b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_MC_GV11B_H #define NVGPU_HW_MC_GV11B_H +#include + static inline u32 mc_boot_0_r(void) { return 0x00000000U; @@ -142,7 +144,7 @@ static inline u32 mc_enable_pmedia_f(u32 v) } static inline u32 mc_enable_pmedia_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 mc_enable_pmedia_v(u32 r) { @@ -150,7 +152,7 @@ static inline u32 mc_enable_pmedia_v(u32 r) } static inline u32 mc_enable_ce0_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 mc_enable_pfifo_enabled_f(void) { @@ -178,7 +180,7 @@ static inline u32 mc_enable_pfb_enabled_f(void) } static inline u32 mc_enable_ce2_m(void) { - return 0x1U << 21U; + return U32(0x1U) << 21U; } static inline u32 mc_enable_ce2_enabled_f(void) { @@ -214,7 +216,7 @@ static inline u32 mc_enable_pb_0_f(u32 v) } static inline u32 mc_enable_pb_0_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 mc_enable_pb_0_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index f5e3d6c4b..be1f38850 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_PBDMA_GV11B_H #define NVGPU_HW_PBDMA_GV11B_H +#include + static inline u32 pbdma_gp_entry1_r(void) { return 0x10000004U; @@ -514,7 +516,7 @@ static inline u32 pbdma_intr_1_r(u32 i) } static inline u32 pbdma_intr_1_ctxnotvalid_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) { @@ -638,7 +640,7 @@ static inline u32 pbdma_timeout_r(u32 i) } static inline u32 pbdma_timeout_period_m(void) { - return 0xffffffffU << 0U; + return U32(0xffffffffU) << 0U; } static inline u32 pbdma_timeout_period_max_f(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h index 2226b95d7..48e8f51ed 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_PERF_GV11B_H #define NVGPU_HW_PERF_GV11B_H +#include + static inline u32 perf_pmmgpc_perdomain_offset_v(void) { return 0x00000200U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h index b3cc98386..fd4b45543 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_PRAM_GV11B_H #define NVGPU_HW_PRAM_GV11B_H +#include + static inline u32 pram_data032_r(u32 i) { return 0x00700000U + i*4U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h index c053253ae..ae3d078b0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -56,13 +56,15 @@ #ifndef NVGPU_HW_PRI_RINGMASTER_GV11B_H #define NVGPU_HW_PRI_RINGMASTER_GV11B_H +#include + static inline u32 pri_ringmaster_command_r(void) { return 0x0012004cU; } static inline u32 pri_ringmaster_command_cmd_m(void) { - return 0x3fU << 0U; + return U32(0x3fU) << 0U; } static inline u32 pri_ringmaster_command_cmd_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h index d7c6cae7a..5fff19a56 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_PRI_RINGSTATION_GPC_GV11B_H #define NVGPU_HW_PRI_RINGSTATION_GPC_GV11B_H +#include + static inline u32 pri_ringstation_gpc_master_config_r(u32 i) { return 0x00128300U + i*4U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index 1b3c86621..a50db285c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GV11B_H #define NVGPU_HW_PRI_RINGSTATION_SYS_GV11B_H +#include + static inline u32 pri_ringstation_sys_master_config_r(u32 i) { return 0x00122300U + i*4U; @@ -66,7 +68,7 @@ static inline u32 pri_ringstation_sys_decode_config_r(void) } static inline u32 pri_ringstation_sys_decode_config_ring_m(void) { - return 0x7U << 0U; + return U32(0x7U) << 0U; } static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 9bbce3545..e5e9b5daa 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_PROJ_GV11B_H #define NVGPU_HW_PROJ_GV11B_H +#include + static inline u32 proj_gpc_base_v(void) { return 0x00500000U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 1d0ac472b..b51cc7a44 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_PWR_GV11B_H #define NVGPU_HW_PWR_GV11B_H +#include + static inline u32 pwr_falcon_irqsset_r(void) { return 0x0010a000U; @@ -102,7 +104,7 @@ static inline u32 pwr_pmu_ecc_intr_status_corrected_f(u32 v) } static inline u32 pwr_pmu_ecc_intr_status_corrected_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 pwr_pmu_ecc_intr_status_uncorrected_f(u32 v) { @@ -110,7 +112,7 @@ static inline u32 pwr_pmu_ecc_intr_status_uncorrected_f(u32 v) } static inline u32 pwr_pmu_ecc_intr_status_uncorrected_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 pwr_falcon_irqmode_r(void) { @@ -462,7 +464,7 @@ static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) } static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) { @@ -474,7 +476,7 @@ static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) { - return 0x1U << 6U; + return U32(0x1U) << 6U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) { @@ -498,7 +500,7 @@ static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) } static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) { - return 0x1U << 20U; + return U32(0x1U) << 20U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) { @@ -550,11 +552,11 @@ static inline u32 pwr_falcon_dmactl_r(void) } static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 pwr_falcon_hwcfg_r(void) { @@ -614,7 +616,7 @@ static inline u32 pwr_falcon_exterrstat_r(void) } static inline u32 pwr_falcon_exterrstat_valid_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) { @@ -638,7 +640,7 @@ static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) } static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) { - return 0xfU << 0U; + return U32(0xfU) << 0U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) { @@ -670,7 +672,7 @@ static inline u32 pwr_falcon_dmemc_offs_f(u32 v) } static inline u32 pwr_falcon_dmemc_offs_m(void) { - return 0x3fU << 2U; + return U32(0x3fU) << 2U; } static inline u32 pwr_falcon_dmemc_blk_f(u32 v) { @@ -678,7 +680,7 @@ static inline u32 pwr_falcon_dmemc_blk_f(u32 v) } static inline u32 pwr_falcon_dmemc_blk_m(void) { - return 0xffU << 8U; + return U32(0xffU) << 8U; } static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) { @@ -742,7 +744,7 @@ static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) } static inline u32 pwr_pmu_mutex_id_release_value_m(void) { - return 0xffU << 0U; + return U32(0xffU) << 0U; } static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) { @@ -862,7 +864,7 @@ static inline u32 pwr_pmu_idle_ctrl_r(u32 i) } static inline u32 pwr_pmu_idle_ctrl_value_m(void) { - return 0x3U << 0U; + return U32(0x3U) << 0U; } static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) { @@ -874,7 +876,7 @@ static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) } static inline u32 pwr_pmu_idle_ctrl_filter_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) { @@ -958,7 +960,7 @@ static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_f(u32 v) } static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_f(u32 v) { @@ -966,7 +968,7 @@ static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_f(u32 v) } static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_m(void) { - return 0x1U << 1U; + return U32(0x1U) << 1U; } static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_f(u32 v) { @@ -974,7 +976,7 @@ static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_f(u32 v) } static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m(void) { - return 0x1U << 8U; + return U32(0x1U) << 8U; } static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) { @@ -982,7 +984,7 @@ static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) } static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m(void) { - return 0x1U << 9U; + return U32(0x1U) << 9U; } static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { @@ -990,7 +992,7 @@ static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow } static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { @@ -998,7 +1000,7 @@ static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overfl } static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1U << 18U; + return U32(0x1U) << 18U; } static inline u32 pwr_pmu_falcon_ecc_status_reset_f(u32 v) { @@ -1038,7 +1040,7 @@ static inline u32 pwr_pmu_falcon_ecc_address_row_address_f(u32 v) } static inline u32 pwr_pmu_falcon_ecc_address_row_address_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 pwr_pmu_falcon_ecc_address_row_address_v(u32 r) { @@ -1058,7 +1060,7 @@ static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_f(u32 v) } static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_v(u32 r) { @@ -1074,7 +1076,7 @@ static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_f(u32 v) } static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_v(u32 r) { @@ -1094,7 +1096,7 @@ static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_f(u32 v) } static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_m(void) { - return 0xffffU << 0U; + return U32(0xffffU) << 0U; } static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_v(u32 r) { @@ -1110,7 +1112,7 @@ static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) } static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffffU << 16U; + return U32(0xffffU) << 16U; } static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { @@ -1142,7 +1144,7 @@ static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) } static inline u32 pwr_fbif_transcfg_mem_type_m(void) { - return 0x1U << 2U; + return U32(0x1U) << 2U; } static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index 067594ab1..2802b0570 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_RAM_GV11B_H #define NVGPU_HW_RAM_GV11B_H +#include + static inline u32 ram_in_ramfc_s(void) { return 4096U; @@ -102,7 +104,7 @@ static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) } static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) { @@ -118,7 +120,7 @@ static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) } static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) { - return 0x1U << 5U; + return U32(0x1U) << 5U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) { @@ -134,7 +136,7 @@ static inline u32 ram_in_use_ver2_pt_format_f(u32 v) } static inline u32 ram_in_use_ver2_pt_format_m(void) { - return 0x1U << 10U; + return U32(0x1U) << 10U; } static inline u32 ram_in_use_ver2_pt_format_w(void) { @@ -154,7 +156,7 @@ static inline u32 ram_in_big_page_size_f(u32 v) } static inline u32 ram_in_big_page_size_m(void) { - return 0x1U << 11U; + return U32(0x1U) << 11U; } static inline u32 ram_in_big_page_size_w(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index 3f553e683..8c2c421dc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_THERM_GV11B_H #define NVGPU_HW_THERM_GV11B_H +#include + static inline u32 therm_use_a_r(void) { return 0x00020798U; @@ -186,7 +188,7 @@ static inline u32 therm_config2_grad_step_duration_f(u32 v) } static inline u32 therm_config2_grad_step_duration_m(void) { - return 0xfU << 8U; + return U32(0xfU) << 8U; } static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) { @@ -202,7 +204,7 @@ static inline u32 therm_gate_ctrl_r(u32 i) } static inline u32 therm_gate_ctrl_eng_clk_m(void) { - return 0x3U << 0U; + return U32(0x3U) << 0U; } static inline u32 therm_gate_ctrl_eng_clk_run_f(void) { @@ -218,7 +220,7 @@ static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) } static inline u32 therm_gate_ctrl_blk_clk_m(void) { - return 0x3U << 2U; + return U32(0x3U) << 2U; } static inline u32 therm_gate_ctrl_blk_clk_run_f(void) { @@ -230,7 +232,7 @@ static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) } static inline u32 therm_gate_ctrl_idle_holdoff_m(void) { - return 0x1U << 4U; + return U32(0x1U) << 4U; } static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) { @@ -246,7 +248,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) } static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) { - return 0x1fU << 8U; + return U32(0x1fU) << 8U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) { @@ -258,7 +260,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) { - return 0x7U << 13U; + return U32(0x7U) << 13U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) { @@ -270,7 +272,7 @@ static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) } static inline u32 therm_gate_ctrl_eng_delay_before_m(void) { - return 0xfU << 16U; + return U32(0xfU) << 16U; } static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) { @@ -282,7 +284,7 @@ static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) } static inline u32 therm_gate_ctrl_eng_delay_after_m(void) { - return 0xfU << 20U; + return U32(0xfU) << 20U; } static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) { @@ -294,7 +296,7 @@ static inline u32 therm_fecs_idle_filter_r(void) } static inline u32 therm_fecs_idle_filter_value_m(void) { - return 0xffffffffU << 0U; + return U32(0xffffffffU) << 0U; } static inline u32 therm_fecs_idle_filter_value__prod_f(void) { @@ -306,7 +308,7 @@ static inline u32 therm_hubmmu_idle_filter_r(void) } static inline u32 therm_hubmmu_idle_filter_value_m(void) { - return 0xffffffffU << 0U; + return U32(0xffffffffU) << 0U; } static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) { @@ -322,7 +324,7 @@ static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) } static inline u32 therm_clk_slowdown_idle_factor_m(void) { - return 0x3fU << 16U; + return U32(0x3fU) << 16U; } static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) { @@ -374,7 +376,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) } static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) { - return 0x3fU << 0U; + return U32(0x3fU) << 0U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1_f(void) { @@ -410,7 +412,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) } static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) { - return 0x3fU << 6U; + return U32(0x3fU) << 6U; } static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) { @@ -418,7 +420,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) } static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) { - return 0x3fU << 12U; + return U32(0x3fU) << 12U; } static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) { @@ -426,7 +428,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) } static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) { - return 0x3fU << 18U; + return U32(0x3fU) << 18U; } static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) { @@ -434,7 +436,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) } static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) { - return 0x3fU << 24U; + return U32(0x3fU) << 24U; } static inline u32 therm_grad_stepping0_r(void) { @@ -450,7 +452,7 @@ static inline u32 therm_grad_stepping0_feature_f(u32 v) } static inline u32 therm_grad_stepping0_feature_m(void) { - return 0x1U << 0U; + return U32(0x1U) << 0U; } static inline u32 therm_grad_stepping0_feature_v(u32 r) { @@ -478,7 +480,7 @@ static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) } static inline u32 therm_clk_timing_grad_slowdown_m(void) { - return 0x1U << 16U; + return U32(0x1U) << 16U; } static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h index e74e681a0..5451b9459 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_TIMER_GV11B_H #define NVGPU_HW_TIMER_GV11B_H +#include + static inline u32 timer_pri_timeout_r(void) { return 0x00009080U; @@ -66,7 +68,7 @@ static inline u32 timer_pri_timeout_period_f(u32 v) } static inline u32 timer_pri_timeout_period_m(void) { - return 0xffffffU << 0U; + return U32(0xffffffU) << 0U; } static inline u32 timer_pri_timeout_period_v(u32 r) { @@ -78,7 +80,7 @@ static inline u32 timer_pri_timeout_en_f(u32 v) } static inline u32 timer_pri_timeout_en_m(void) { - return 0x1U << 31U; + return U32(0x1U) << 31U; } static inline u32 timer_pri_timeout_en_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h index 00f54a13f..a0a4ee747 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -56,6 +56,8 @@ #ifndef NVGPU_HW_TOP_GV11B_H #define NVGPU_HW_TOP_GV11B_H +#include + static inline u32 top_num_gpcs_r(void) { return 0x00022430U;