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gpu: nvgpu: add pbdma intr_enable HAL ops.

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A new HAL ops intr_enable() is constructed in
hal.fifo.pbdma unit. The implementation for this HAL ops
is based on gm20b and gv11b architectures.

Jira NVGPU-2950

Change-Id: Ifd9c3bfad4264449c52f411e8cad8674c3756048
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2073536
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2019-03-15 14:34:04 +05:30
committed by mobile promotions
parent ce5c43d24a
commit 52cbc88a00
14 changed files with 113 additions and 52 deletions
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30
drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a.c
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@@ -66,41 +66,19 @@ static u32 gk20a_fifo_intr_0_en_mask(struct gk20a *g)
void gk20a_fifo_intr_0_enable(struct gk20a *g, bool enable)
{
unsigned int i;
u32 intr_stall, mask;
u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
u32 mask;
if (!enable) {
g->ops.fifo.ctxsw_timeout_enable(g, false);
nvgpu_writel(g, fifo_intr_en_0_r(), 0U);
g->ops.fifo.ctxsw_timeout_enable(g, false);
g->ops.pbdma.intr_enable(g, false);
return;
}
/* Enable interrupts */
g->ops.fifo.ctxsw_timeout_enable(g, true);
/* clear and enable pbdma interrupt */
for (i = 0; i < host_num_pbdma; i++) {
nvgpu_writel(g, pbdma_intr_0_r(i), U32_MAX);
nvgpu_writel(g, pbdma_intr_1_r(i), U32_MAX);
intr_stall = nvgpu_readl(g, pbdma_intr_stall_r(i));
intr_stall &= ~pbdma_intr_stall_lbreq_enabled_f();
nvgpu_writel(g, pbdma_intr_stall_r(i), intr_stall);
nvgpu_log_info(g, "pbdma id:%u, intr_en_0 0x%08x", i,
intr_stall);
nvgpu_writel(g, pbdma_intr_en_0_r(i), intr_stall);
intr_stall = nvgpu_readl(g, pbdma_intr_stall_1_r(i));
/*
* For bug 2082123
* Mask the unused HCE_RE_ILLEGAL_OP bit from the interrupt.
*/
intr_stall &= ~pbdma_intr_stall_1_hce_illegal_op_enabled_f();
nvgpu_log_info(g, "pbdma id:%u, intr_en_1 0x%08x", i,
intr_stall);
nvgpu_writel(g, pbdma_intr_en_1_r(i), intr_stall);
}
g->ops.pbdma.intr_enable(g, true);
/* reset runlist interrupts */
nvgpu_writel(g, fifo_intr_runlist_r(), ~U32(0U));