diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
index 1582f1dee..c5e4b71b3 100644
--- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c
+++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
@@ -28,24 +28,12 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/soc.h>
 #include <nvgpu/enabled.h>
-#include <nvgpu/fifo.h>
-#include <nvgpu/acr.h>
-#include <nvgpu/pmu.h>
-#include <nvgpu/ce.h>
 #include <nvgpu/gmmu.h>
-#include <nvgpu/ltc.h>
-#include <nvgpu/cbc.h>
-#include <nvgpu/ecc.h>
-#include <nvgpu/fbp.h>
 #include <nvgpu/vidmem.h>
-#include <nvgpu/mm.h>
 #include <nvgpu/soc.h>
-#include <nvgpu/clk_arb.h>
-#include <nvgpu/therm.h>
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel_sync.h>
-#include <nvgpu/gr/gr.h>
 #include <nvgpu/nvgpu_init.h>
 
 #ifdef CONFIG_NVGPU_TRACE
@@ -101,45 +89,47 @@ int nvgpu_prepare_poweroff(struct gk20a *g)
 #ifdef CONFIG_NVGPU_LS_PMU
 	/* disable elpg before gr or fifo suspend */
 	if (g->support_ls_pmu) {
-		ret = nvgpu_pmu_destroy(g, g->pmu);
+		ret = g->ops.pmu.pmu_destroy(g, g->pmu);
 	}
 #endif
 
 #ifdef CONFIG_NVGPU_DGPU
 	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) {
-		tmp_ret = nvgpu_sec2_destroy(g);
+		tmp_ret = g->ops.sec2.sec2_destroy(g);
 		if ((tmp_ret != 0) && (ret == 0)) {
 			ret = tmp_ret;
 		}
 	}
 #endif
-	tmp_ret = nvgpu_gr_suspend(g);
+	tmp_ret = g->ops.gr.gr_suspend(g);
 	if ((tmp_ret != 0) && (ret == 0)) {
 		ret = tmp_ret;
 	}
-	tmp_ret = nvgpu_mm_suspend(g);
+	tmp_ret = g->ops.mm.mm_suspend(g);
 	if ((tmp_ret != 0) && (ret == 0)) {
 		ret = tmp_ret;
 	}
-	tmp_ret = nvgpu_fifo_suspend(g);
+	tmp_ret = g->ops.fifo.fifo_suspend(g);
 	if ((tmp_ret != 0) && (ret == 0)) {
 		ret = tmp_ret;
 	}
 
-	nvgpu_falcon_sw_free(g, FALCON_ID_PMU);
-	nvgpu_falcon_sw_free(g, FALCON_ID_FECS);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_PMU);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_FECS);
 
 #ifdef CONFIG_NVGPU_DGPU
-	nvgpu_falcon_sw_free(g, FALCON_ID_GSPLITE);
-	nvgpu_falcon_sw_free(g, FALCON_ID_NVDEC);
-	nvgpu_falcon_sw_free(g, FALCON_ID_SEC2);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_GSPLITE);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVDEC);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_SEC2);
 
-	nvgpu_ce_app_suspend(g);
+	g->ops.ce.ce_app_suspend(g);
 #endif
 
 #ifdef CONFIG_NVGPU_DGPU
-	/* deinit the bios */
-	nvgpu_bios_sw_deinit(g, g->bios);
+	if (g->ops.bios.bios_sw_deinit != NULL) {
+		/* deinit the bios */
+		g->ops.bios.bios_sw_deinit(g, g->bios);
+	}
 #endif
 
 	/* Disable GPCPLL */
@@ -189,45 +179,45 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 	 * Do this early so any early VMs that get made are capable of mapping
 	 * buffers.
 	 */
-	err = nvgpu_pd_cache_init(g);
+	err = g->ops.mm.pd_cache_init(g);
 	if (err != 0) {
 		return err;
 	}
 
 	/* init interface layer support for PMU falcon */
-	err = nvgpu_falcon_sw_init(g, FALCON_ID_PMU);
+	err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_PMU);
 	if (err != 0) {
 		nvgpu_err(g, "failed to sw init FALCON_ID_PMU");
 		goto exit;
 	}
 
-	err = nvgpu_falcon_sw_init(g, FALCON_ID_FECS);
+	err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_FECS);
 	if (err != 0) {
 		nvgpu_err(g, "failed to sw init FALCON_ID_FECS");
 		goto done_pmu;
 	}
 
 #ifdef CONFIG_NVGPU_DGPU
-	err = nvgpu_falcon_sw_init(g, FALCON_ID_SEC2);
+	err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_SEC2);
 	if (err != 0) {
 		nvgpu_err(g, "failed to sw init FALCON_ID_SEC2");
 		goto done_fecs;
 	}
 
-	err = nvgpu_falcon_sw_init(g, FALCON_ID_NVDEC);
+	err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_NVDEC);
 	if (err != 0) {
 		nvgpu_err(g, "failed to sw init FALCON_ID_NVDEC");
 		goto done_sec2;
 	}
 
-	err = nvgpu_falcon_sw_init(g, FALCON_ID_GSPLITE);
+	err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_GSPLITE);
 	if (err != 0) {
 		nvgpu_err(g, "failed to sw init FALCON_ID_GSPLITE");
 		goto done_nvdec;
 	}
 #endif
 
-	err = nvgpu_pmu_early_init(g, &g->pmu);
+	err = g->ops.pmu.pmu_early_init(g, &g->pmu);
 	if (err != 0) {
 		nvgpu_err(g, "failed to early init pmu sw");
 		goto done;
@@ -235,7 +225,7 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 
 #ifdef CONFIG_NVGPU_DGPU
 	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) {
-		err = nvgpu_init_sec2_setup_sw(g, &g->sec2);
+		err = g->ops.sec2.init_sec2_setup_sw(g, &g->sec2);
 		if (err != 0) {
 			nvgpu_err(g, "failed to init sec2 sw setup");
 			goto done;
@@ -244,7 +234,7 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 #endif
 	if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
 		/* Init chip specific ACR properties */
-		err = nvgpu_acr_init(g, &g->acr);
+		err = g->ops.acr.acr_init(g, &g->acr);
 		if (err != 0) {
 			nvgpu_err(g, "ACR init failed %d", err);
 			goto done;
@@ -252,7 +242,7 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 	}
 
 #ifdef CONFIG_NVGPU_DGPU
-	err = nvgpu_bios_sw_init(g, &g->bios);
+	err = g->ops.bios.bios_sw_init(g, &g->bios);
 	if (err != 0) {
 		nvgpu_err(g, "BIOS SW init failed %d", err);
 		goto done;
@@ -311,19 +301,19 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 		goto done;
 	}
 
-	err = nvgpu_init_ltc_support(g);
+	err = g->ops.ltc.init_ltc_support(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init ltc");
 		goto done;
 	}
 
-	err = nvgpu_init_mm_support(g);
+	err = g->ops.mm.init_mm_support(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init gk20a mm");
 		goto done;
 	}
 
-	err = nvgpu_fifo_init_support(g);
+	err = g->ops.fifo.fifo_init_support(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init gk20a fifo");
 		goto done;
@@ -367,14 +357,14 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 #endif
 
 	/* prepare portion of sw required for enable hw */
-	err = nvgpu_gr_prepare_sw(g);
+	err = g->ops.gr.gr_prepare_sw(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to prepare sw");
 		nvgpu_mutex_release(&g->tpc_pg_lock);
 		goto done;
 	}
 
-	err = nvgpu_gr_enable_hw(g);
+	err = g->ops.gr.gr_enable_hw(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to enable gr");
 		nvgpu_mutex_release(&g->tpc_pg_lock);
@@ -383,7 +373,7 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 
 	if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
 		/* construct ucode blob, load & bootstrap LSF's using HS ACR */
-		err = nvgpu_acr_construct_execute(g, g->acr);
+		err = g->ops.acr.acr_construct_execute(g, g->acr);
 		if (err != 0) {
 			nvgpu_mutex_release(&g->tpc_pg_lock);
 			goto done;
@@ -392,7 +382,7 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 
 #ifdef CONFIG_NVGPU_DGPU
 	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) {
-		err = nvgpu_init_sec2_support(g);
+		err = g->ops.sec2.init_sec2_support(g);
 		if (err != 0) {
 			nvgpu_err(g, "failed to init sec2");
 			nvgpu_mutex_release(&g->tpc_pg_lock);
@@ -402,7 +392,7 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 #endif
 
 #ifdef CONFIG_NVGPU_LS_PMU
-	err = nvgpu_pmu_init(g, g->pmu);
+	err = g->ops.pmu.pmu_init(g, g->pmu);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init gk20a pmu");
 		nvgpu_mutex_release(&g->tpc_pg_lock);
@@ -410,39 +400,41 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 	}
 #endif
 
-	err = nvgpu_fbp_init_support(g);
+	err = g->ops.fbp.fbp_init_support(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init gk20a fbp");
 		nvgpu_mutex_release(&g->tpc_pg_lock);
 		goto done;
 	}
 
-	err = nvgpu_gr_init_support(g);
+	err = g->ops.gr.gr_init_support(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init gk20a gr");
 		nvgpu_mutex_release(&g->tpc_pg_lock);
 		goto done;
 	}
 
-	err = nvgpu_ecc_init_support(g);
-	if (err != 0) {
-		nvgpu_err(g, "failed to init ecc");
-		nvgpu_mutex_release(&g->tpc_pg_lock);
-		goto done;
+	if (g->ops.gr.ecc.ecc_init_support != NULL) {
+		err = g->ops.gr.ecc.ecc_init_support(g);
+		if (err != 0) {
+			nvgpu_err(g, "failed to init ecc");
+			nvgpu_mutex_release(&g->tpc_pg_lock);
+			goto done;
+		}
 	}
 
 	nvgpu_mutex_release(&g->tpc_pg_lock);
 
 #ifdef CONFIG_NVGPU_LS_PMU
 	if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) {
-		err = nvgpu_pmu_pstate_sw_setup(g);
+		err = g->ops.pmu.pmu_pstate_sw_setup(g);
 		if (err != 0) {
 			nvgpu_err(g, "failed to init pstates");
 			nvgpu_mutex_release(&g->tpc_pg_lock);
 			goto done;
 		}
 
-		err = nvgpu_pmu_pstate_pmu_setup(g);
+		err = g->ops.pmu.pmu_pstate_pmu_setup(g);
 		if (err != 0) {
 			nvgpu_err(g, "failed to init pstates");
 			goto done;
@@ -460,7 +452,7 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 #endif
 	{
 #ifdef CONFIG_NVGPU_CLK_ARB
-		err = nvgpu_clk_arb_init_arbiter(g);
+		err = g->ops.clk_arb.clk_arb_init_arbiter(g);
 		if (err != 0) {
 			nvgpu_err(g, "failed to init clk arb");
 			goto done;
@@ -468,14 +460,14 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 #endif
 	}
 
-	err = nvgpu_init_therm_support(g);
+	err = g->ops.therm.init_therm_support(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init gk20a therm");
 		goto done;
 	}
 
 #ifdef CONFIG_NVGPU_COMPRESSION
-	err = nvgpu_cbc_init_support(g);
+	err = g->ops.cbc.cbc_init_support(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init cbc");
 		goto done;
@@ -489,14 +481,14 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 	g->ops.fb.set_debug_mode(g, g->mmu_debug_ctrl);
 #endif
 
-	err = nvgpu_ce_init_support(g);
+	err = g->ops.ce.ce_init_support(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init ce");
 		goto done;
 	}
 
 #ifdef CONFIG_NVGPU_DGPU
-	err = nvgpu_ce_app_init_support(g);
+	err = g->ops.ce.ce_app_init_support(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to init ce app");
 		goto done;
@@ -552,16 +544,16 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 
 done:
 #ifdef CONFIG_NVGPU_DGPU
-	nvgpu_falcon_sw_free(g, FALCON_ID_GSPLITE);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_GSPLITE);
 done_nvdec:
-	nvgpu_falcon_sw_free(g, FALCON_ID_NVDEC);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVDEC);
 done_sec2:
-	nvgpu_falcon_sw_free(g, FALCON_ID_SEC2);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_SEC2);
 done_fecs:
 #endif
-	nvgpu_falcon_sw_free(g, FALCON_ID_FECS);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_FECS);
 done_pmu:
-	nvgpu_falcon_sw_free(g, FALCON_ID_PMU);
+	g->ops.falcon.falcon_sw_free(g, FALCON_ID_PMU);
 exit:
 	if (err != 0) {
 		g->power_on = false;
@@ -653,20 +645,28 @@ static void gk20a_free_cb(struct nvgpu_ref *refcount)
 	nvgpu_log(g, gpu_dbg_shutdown, "Freeing GK20A struct!");
 
 #ifdef CONFIG_NVGPU_DGPU
-	nvgpu_ce_app_destroy(g);
+	if (g->ops.ce.ce_app_destroy != NULL) {
+		g->ops.ce.ce_app_destroy(g);
+	}
 #endif
 
 #ifdef CONFIG_NVGPU_COMPRESSION
-	nvgpu_cbc_remove_support(g);
+	if (g->ops.cbc.cbc_remove_support != NULL) {
+		g->ops.cbc.cbc_remove_support(g);
+	}
 #endif
 
-	nvgpu_ecc_remove_support(g);
+	if (g->ops.gr.ecc.ecc_remove_support != NULL) {
+		g->ops.gr.ecc.ecc_remove_support(g);
+	}
 
 	if (g->remove_support != NULL) {
 		g->remove_support(g);
 	}
 
-	nvgpu_ltc_remove_support(g);
+	if (g->ops.ltc.ltc_remove_support != NULL) {
+		g->ops.ltc.ltc_remove_support(g);
+	}
 
 	if (g->gfree != NULL) {
 		g->gfree(g);
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
index 141af8306..d214e6c8d 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
@@ -45,6 +45,15 @@
 #endif
 #include <nvgpu/gr/fecs_trace.h>
 #include <nvgpu/nvgpu_init.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/ce.h>
+#include <nvgpu/pmu.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_pstate.h>
+#endif
+#include <nvgpu/fbp.h>
+#include <nvgpu/therm.h>
+#include <nvgpu/clk_arb.h>
 
 #include "hal/mm/mm_gk20a.h"
 #include "hal/mm/mm_gm20b.h"
@@ -122,7 +131,18 @@
 #define PRIV_SECURITY_DISABLE 0x01
 
 static const struct gpu_ops gm20b_ops = {
+	.acr = {
+		.acr_init = nvgpu_acr_init,
+		.acr_construct_execute = nvgpu_acr_construct_execute,
+	},
+#ifdef CONFIG_NVGPU_DGPU
+	.bios = {
+		.bios_sw_init = nvgpu_bios_sw_init,
+	},
+#endif /* CONFIG_NVGPU_DGPU */
 	.ltc = {
+		.init_ltc_support = nvgpu_init_ltc_support,
+		.ltc_remove_support = nvgpu_ltc_remove_support,
 		.determine_L2_size_bytes = gm20b_determine_L2_size_bytes,
 		.init_fs_state = gm20b_ltc_init_fs_state,
 		.flush = gm20b_flush_ltc,
@@ -146,6 +166,8 @@ static const struct gpu_ops gm20b_ops = {
 	},
 #ifdef CONFIG_NVGPU_COMPRESSION
 	.cbc = {
+		.cbc_init_support = nvgpu_cbc_init_support,
+		.cbc_remove_support = nvgpu_cbc_remove_support,
 		.init = gm20b_cbc_init,
 		.ctrl = gm20b_cbc_ctrl,
 		.alloc_comptags = gm20b_cbc_alloc_comptags,
@@ -153,10 +175,20 @@ static const struct gpu_ops gm20b_ops = {
 	},
 #endif
 	.ce = {
+		.ce_init_support = nvgpu_ce_init_support,
+#ifdef CONFIG_NVGPU_DGPU
+		.ce_app_init_support = nvgpu_ce_app_init_support,
+		.ce_app_suspend = nvgpu_ce_app_suspend,
+		.ce_app_destroy = nvgpu_ce_app_destroy,
+#endif
 		.isr_stall = gk20a_ce2_stall_isr,
 		.isr_nonstall = gk20a_ce2_nonstall_isr,
 	},
 	.gr = {
+		.gr_prepare_sw = nvgpu_gr_prepare_sw,
+		.gr_enable_hw = nvgpu_gr_enable_hw,
+		.gr_init_support = nvgpu_gr_init_support,
+		.gr_suspend = nvgpu_gr_suspend,
 #ifdef CONFIG_NVGPU_DEBUGGER
 		.get_gr_status = gr_gm20b_get_gr_status,
 		.set_alpha_circular_buffer_size =
@@ -601,6 +633,8 @@ static const struct gpu_ops gm20b_ops = {
 			gr_gm20b_pg_gr_load_gating_prod,
 	},
 	.fifo = {
+		.fifo_init_support = nvgpu_fifo_init_support,
+		.fifo_suspend = nvgpu_fifo_suspend,
 		.init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
 		.preempt_channel = gk20a_fifo_preempt_channel,
 		.preempt_tsg = gk20a_fifo_preempt_tsg,
@@ -798,6 +832,9 @@ static const struct gpu_ops gm20b_ops = {
 		.is_fw_defined = gm20b_netlist_is_firmware_defined,
 	},
 	.mm = {
+		.init_mm_support = nvgpu_init_mm_support,
+		.pd_cache_init = nvgpu_pd_cache_init,
+		.mm_suspend = nvgpu_mm_suspend,
 		.vm_bind_channel = nvgpu_vm_bind_channel,
 		.setup_hw = nvgpu_mm_setup_hw,
 		.is_bar1_supported = gm20b_mm_is_bar1_supported,
@@ -825,6 +862,7 @@ static const struct gpu_ops gm20b_ops = {
 		}
 	},
 	.therm = {
+		.init_therm_support = nvgpu_init_therm_support,
 		.init_therm_setup_hw = gm20b_init_therm_setup_hw,
 		.init_elcg_mode = gm20b_therm_init_elcg_mode,
 		.init_blcg_mode = gm20b_therm_init_blcg_mode,
@@ -836,6 +874,13 @@ static const struct gpu_ops gm20b_ops = {
 	},
 #ifdef CONFIG_NVGPU_LS_PMU
 	.pmu = {
+		/* Init */
+		.pmu_init = nvgpu_pmu_init,
+		.pmu_pstate_sw_setup = nvgpu_pmu_pstate_sw_setup,
+		.pmu_pstate_pmu_setup = nvgpu_pmu_pstate_pmu_setup,
+		.pmu_destroy = nvgpu_pmu_destroy,
+		.pmu_early_init = nvgpu_pmu_early_init,
+
 		.is_pmu_supported = gm20b_is_pmu_supported,
 		.falcon_base_addr = gk20a_pmu_falcon_base_addr,
 		.pmu_reset = nvgpu_pmu_reset,
@@ -876,6 +921,11 @@ static const struct gpu_ops gm20b_ops = {
 		.setup_apertures = gm20b_pmu_setup_apertures,
 		.secured_pmu_start = gm20b_secured_pmu_start,
 	},
+#endif
+#ifdef CONFIG_NVGPU_CLK_ARB
+	.clk_arb = {
+		.clk_arb_init_arbiter = nvgpu_clk_arb_init_arbiter,
+	},
 #endif
 	.clk = {
 		.init_clk_support = gm20b_init_clk_support,
@@ -985,6 +1035,8 @@ static const struct gpu_ops gm20b_ops = {
 	},
 #endif
 	.falcon = {
+		.falcon_sw_init = nvgpu_falcon_sw_init,
+		.falcon_sw_free = nvgpu_falcon_sw_free,
 		.reset = gk20a_falcon_reset,
 		.is_falcon_cpu_halted =  gk20a_is_falcon_cpu_halted,
 		.is_falcon_idle =  gk20a_is_falcon_idle,
@@ -1008,6 +1060,9 @@ static const struct gpu_ops gm20b_ops = {
 		.get_falcon_ctls = gk20a_falcon_get_ctls,
 #endif
 	},
+	.fbp = {
+		.fbp_init_support = nvgpu_fbp_init_support,
+	},
 	.priv_ring = {
 		.enable_priv_ring = gm20b_priv_ring_enable,
 		.isr = gm20b_priv_ring_isr,
@@ -1063,6 +1118,12 @@ int gm20b_init_hal(struct gk20a *g)
 	return -EINVAL;
 #endif
 
+	gops->acr = gm20b_ops.acr;
+	gops->bios = gm20b_ops.bios;
+	gops->fbp = gm20b_ops.fbp;
+#ifdef CONFIG_NVGPU_CLK_ARB
+	gops->clk_arb = gm20b_ops.clk_arb;
+#endif
 	gops->ltc = gm20b_ops.ltc;
 #ifdef CONFIG_NVGPU_COMPRESSION
 	gops->cbc = gm20b_ops.cbc;
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
index c87ecb8c3..42eb6b8c3 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
@@ -45,6 +45,15 @@
 #include <nvgpu/pmu/pmu_perfmon.h>
 #endif
 #include <nvgpu/nvgpu_init.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/ce.h>
+#include <nvgpu/pmu.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_pstate.h>
+#endif
+#include <nvgpu/fbp.h>
+#include <nvgpu/therm.h>
+#include <nvgpu/clk_arb.h>
 
 #include "hal/mm/mm_gk20a.h"
 #include "hal/mm/mm_gm20b.h"
@@ -151,7 +160,18 @@ static void gp10b_init_gpu_characteristics(struct gk20a *g)
 }
 
 static const struct gpu_ops gp10b_ops = {
+	.acr = {
+		.acr_init = nvgpu_acr_init,
+		.acr_construct_execute = nvgpu_acr_construct_execute,
+	},
+#ifdef CONFIG_NVGPU_DGPU
+	.bios = {
+		.bios_sw_init = nvgpu_bios_sw_init,
+	},
+#endif /* CONFIG_NVGPU_DGPU */
 	.ltc = {
+		.init_ltc_support = nvgpu_init_ltc_support,
+		.ltc_remove_support = nvgpu_ltc_remove_support,
 		.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
 		.init_fs_state = gp10b_ltc_init_fs_state,
 		.flush = gm20b_flush_ltc,
@@ -175,6 +195,8 @@ static const struct gpu_ops gp10b_ops = {
 	},
 #ifdef CONFIG_NVGPU_COMPRESSION
 	.cbc = {
+		.cbc_init_support = nvgpu_cbc_init_support,
+		.cbc_remove_support = nvgpu_cbc_remove_support,
 		.init = gm20b_cbc_init,
 		.alloc_comptags = gp10b_cbc_alloc_comptags,
 		.ctrl = gp10b_cbc_ctrl,
@@ -182,10 +204,20 @@ static const struct gpu_ops gp10b_ops = {
 	},
 #endif
 	.ce = {
+		.ce_init_support = nvgpu_ce_init_support,
+#ifdef CONFIG_NVGPU_DGPU
+		.ce_app_init_support = nvgpu_ce_app_init_support,
+		.ce_app_suspend = nvgpu_ce_app_suspend,
+		.ce_app_destroy = nvgpu_ce_app_destroy,
+#endif
 		.isr_stall = gp10b_ce_stall_isr,
 		.isr_nonstall = gp10b_ce_nonstall_isr,
 	},
 	.gr = {
+		.gr_prepare_sw = nvgpu_gr_prepare_sw,
+		.gr_enable_hw = nvgpu_gr_enable_hw,
+		.gr_init_support = nvgpu_gr_init_support,
+		.gr_suspend = nvgpu_gr_suspend,
 #ifdef CONFIG_NVGPU_DEBUGGER
 		.get_gr_status = gr_gm20b_get_gr_status,
 		.set_alpha_circular_buffer_size =
@@ -236,6 +268,8 @@ static const struct gpu_ops gp10b_ops = {
 		.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 		.ecc = {
+			.ecc_init_support = nvgpu_ecc_init_support,
+			.ecc_remove_support = nvgpu_ecc_remove_support,
 			.detect = gp10b_ecc_detect_enabled_units,
 			.init = gp10b_ecc_init,
 		},
@@ -670,6 +704,8 @@ static const struct gpu_ops gp10b_ops = {
 			gr_gp10b_pg_gr_load_gating_prod,
 	},
 	.fifo = {
+		.fifo_init_support = nvgpu_fifo_init_support,
+		.fifo_suspend = nvgpu_fifo_suspend,
 		.init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
 		.preempt_channel = gk20a_fifo_preempt_channel,
 		.preempt_tsg = gk20a_fifo_preempt_tsg,
@@ -884,6 +920,9 @@ static const struct gpu_ops gp10b_ops = {
 		.is_fw_defined = gp10b_netlist_is_firmware_defined,
 	},
 	.mm = {
+		.init_mm_support = nvgpu_init_mm_support,
+		.pd_cache_init = nvgpu_pd_cache_init,
+		.mm_suspend = nvgpu_mm_suspend,
 		.vm_bind_channel = nvgpu_vm_bind_channel,
 		.setup_hw = nvgpu_mm_setup_hw,
 		.is_bar1_supported = gm20b_mm_is_bar1_supported,
@@ -913,6 +952,7 @@ static const struct gpu_ops gp10b_ops = {
 		}
 	},
 	.therm = {
+		.init_therm_support = nvgpu_init_therm_support,
 		.init_therm_setup_hw = gp10b_init_therm_setup_hw,
 		.init_elcg_mode = gm20b_therm_init_elcg_mode,
 		.init_blcg_mode = gm20b_therm_init_blcg_mode,
@@ -920,6 +960,12 @@ static const struct gpu_ops gp10b_ops = {
 	},
 #ifdef CONFIG_NVGPU_LS_PMU
 	.pmu = {
+		/* Init */
+		.pmu_early_init = nvgpu_pmu_early_init,
+		.pmu_init = nvgpu_pmu_init,
+		.pmu_pstate_sw_setup = nvgpu_pmu_pstate_sw_setup,
+		.pmu_pstate_pmu_setup = nvgpu_pmu_pstate_pmu_setup,
+		.pmu_destroy = nvgpu_pmu_destroy,
 		.is_pmu_supported = gp10b_is_pmu_supported,
 		.falcon_base_addr = gk20a_pmu_falcon_base_addr,
 		.setup_apertures = gm20b_pmu_setup_apertures,
@@ -963,6 +1009,7 @@ static const struct gpu_ops gp10b_ops = {
 #endif
 #ifdef CONFIG_NVGPU_CLK_ARB
 	.clk_arb = {
+		.clk_arb_init_arbiter = nvgpu_clk_arb_init_arbiter,
 		.check_clk_arb_support = gp10b_check_clk_arb_support,
 		.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
 		.get_arbiter_f_points = gp10b_get_arbiter_f_points,
@@ -1074,6 +1121,8 @@ static const struct gpu_ops gp10b_ops = {
 	},
 #endif
 	.falcon = {
+		.falcon_sw_init = nvgpu_falcon_sw_init,
+		.falcon_sw_free = nvgpu_falcon_sw_free,
 		.reset = gk20a_falcon_reset,
 		.is_falcon_cpu_halted =  gk20a_is_falcon_cpu_halted,
 		.is_falcon_idle =  gk20a_is_falcon_idle,
@@ -1097,6 +1146,9 @@ static const struct gpu_ops gp10b_ops = {
 		.get_falcon_ctls = gk20a_falcon_get_ctls,
 #endif
 	},
+	.fbp = {
+		.fbp_init_support = nvgpu_fbp_init_support,
+	},
 	.priv_ring = {
 		.enable_priv_ring = gm20b_priv_ring_enable,
 		.isr = gp10b_priv_ring_isr,
@@ -1158,6 +1210,9 @@ int gp10b_init_hal(struct gk20a *g)
 	return -EINVAL;
 #endif
 
+	gops->acr = gp10b_ops.acr;
+	gops->bios = gp10b_ops.bios;
+	gops->fbp = gp10b_ops.fbp;
 	gops->ltc = gp10b_ops.ltc;
 #ifdef CONFIG_NVGPU_COMPRESSION
 	gops->cbc = gp10b_ops.cbc;
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 3613614d5..87e7d13dd 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -22,6 +22,15 @@
  * DEALINGS IN THE SOFTWARE.
  */
 #include <nvgpu/gk20a.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/ce.h>
+#include <nvgpu/pmu.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_pstate.h>
+#endif
+#include <nvgpu/fbp.h>
+#include <nvgpu/therm.h>
+#include <nvgpu/clk_arb.h>
 #include <nvgpu/fuse.h>
 #include <nvgpu/pbdma.h>
 #include <nvgpu/engines.h>
@@ -187,7 +196,18 @@ static void gv11b_init_gpu_characteristics(struct gk20a *g)
 }
 
 static const struct gpu_ops gv11b_ops = {
+	.acr = {
+		.acr_init = nvgpu_acr_init,
+		.acr_construct_execute = nvgpu_acr_construct_execute,
+	},
+#ifdef CONFIG_NVGPU_DGPU
+	.bios = {
+		.bios_sw_init = nvgpu_bios_sw_init,
+	},
+#endif /* CONFIG_NVGPU_DGPU */
 	.ltc = {
+		.init_ltc_support = nvgpu_init_ltc_support,
+		.ltc_remove_support = nvgpu_ltc_remove_support,
 #ifdef CONFIG_NVGPU_INJECT_HWERR
 		.get_ltc_err_desc =
 			gv11b_ltc_get_err_desc,
@@ -217,12 +237,20 @@ static const struct gpu_ops gv11b_ops = {
 	},
 #ifdef CONFIG_NVGPU_COMPRESSION
 	.cbc = {
+		.cbc_init_support = nvgpu_cbc_init_support,
+		.cbc_remove_support = nvgpu_cbc_remove_support,
 		.init = gv11b_cbc_init,
 		.alloc_comptags = gp10b_cbc_alloc_comptags,
 		.ctrl = gp10b_cbc_ctrl,
 	},
 #endif
 	.ce = {
+		.ce_init_support = nvgpu_ce_init_support,
+#ifdef CONFIG_NVGPU_DGPU
+		.ce_app_init_support = nvgpu_ce_app_init_support,
+		.ce_app_suspend = nvgpu_ce_app_suspend,
+		.ce_app_destroy = nvgpu_ce_app_destroy,
+#endif
 		.isr_stall = gv11b_ce_stall_isr,
 		.isr_nonstall = gp10b_ce_nonstall_isr,
 		.get_num_pce = gv11b_ce_get_num_pce,
@@ -231,6 +259,10 @@ static const struct gpu_ops gv11b_ops = {
 		.init_prod_values = gv11b_ce_init_prod_values,
 	},
 	.gr = {
+		.gr_prepare_sw = nvgpu_gr_prepare_sw,
+		.gr_enable_hw = nvgpu_gr_enable_hw,
+		.gr_init_support = nvgpu_gr_init_support,
+		.gr_suspend = nvgpu_gr_suspend,
 #ifdef CONFIG_NVGPU_DEBUGGER
 		.get_gr_status = gr_gm20b_get_gr_status,
 		.set_alpha_circular_buffer_size =
@@ -293,6 +325,8 @@ static const struct gpu_ops gv11b_ops = {
 		.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 		.ecc = {
+			.ecc_init_support = nvgpu_ecc_init_support,
+			.ecc_remove_support = nvgpu_ecc_remove_support,
 			.detect = gv11b_ecc_detect_enabled_units,
 			.init = gv11b_ecc_init,
 #ifdef CONFIG_NVGPU_INJECT_HWERR
@@ -836,6 +870,8 @@ static const struct gpu_ops gv11b_ops = {
 			gr_gv11b_pg_gr_load_gating_prod,
 	},
 	.fifo = {
+		.fifo_init_support = nvgpu_fifo_init_support,
+		.fifo_suspend = nvgpu_fifo_suspend,
 		.init_fifo_setup_hw = gv11b_init_fifo_setup_hw,
 		.preempt_channel = gv11b_fifo_preempt_channel,
 		.preempt_tsg = gv11b_fifo_preempt_tsg,
@@ -1058,6 +1094,9 @@ static const struct gpu_ops gv11b_ops = {
 		.is_fw_defined = gv11b_netlist_is_firmware_defined,
 	},
 	.mm = {
+		.init_mm_support = nvgpu_init_mm_support,
+		.pd_cache_init = nvgpu_pd_cache_init,
+		.mm_suspend = nvgpu_mm_suspend,
 		.vm_bind_channel = nvgpu_vm_bind_channel,
 		.setup_hw = nvgpu_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
@@ -1091,6 +1130,7 @@ static const struct gpu_ops gv11b_ops = {
 		}
 	},
 	.therm = {
+		.init_therm_support = nvgpu_init_therm_support,
 		.init_therm_setup_hw = gv11b_init_therm_setup_hw,
 		.init_elcg_mode = gv11b_therm_init_elcg_mode,
 		.init_blcg_mode = gm20b_therm_init_blcg_mode,
@@ -1107,6 +1147,7 @@ static const struct gpu_ops gv11b_ops = {
 		 * ops can be assigned/ignored as per build flag request
 		 */
 		/* Basic init ops */
+		.pmu_early_init = nvgpu_pmu_early_init,
 		.is_pmu_supported = gv11b_is_pmu_supported,
 		.falcon_base_addr = gv11b_pmu_falcon_base_addr,
 		.pmu_reset = nvgpu_pmu_reset,
@@ -1122,6 +1163,11 @@ static const struct gpu_ops gv11b_ops = {
 		.bar0_error_status = gv11b_pmu_bar0_error_status,
 		.validate_mem_integrity = gv11b_pmu_validate_mem_integrity,
 #ifdef CONFIG_NVGPU_LS_PMU
+		/* Init */
+		.pmu_init = nvgpu_pmu_init,
+		.pmu_pstate_sw_setup = nvgpu_pmu_pstate_sw_setup,
+		.pmu_pstate_pmu_setup = nvgpu_pmu_pstate_pmu_setup,
+		.pmu_destroy = nvgpu_pmu_destroy,
 		/* ISR */
 		.pmu_enable_irq = gk20a_pmu_enable_irq,
 		.get_irqdest = gv11b_pmu_get_irqdest,
@@ -1160,6 +1206,7 @@ static const struct gpu_ops gv11b_ops = {
 	},
 #ifdef CONFIG_NVGPU_CLK_ARB
 	.clk_arb = {
+		.clk_arb_init_arbiter = nvgpu_clk_arb_init_arbiter,
 		.check_clk_arb_support = gp10b_check_clk_arb_support,
 		.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
 		.get_arbiter_f_points = gp10b_get_arbiter_f_points,
@@ -1274,6 +1321,8 @@ static const struct gpu_ops gv11b_ops = {
 	},
 #endif
 	.falcon = {
+		.falcon_sw_init = nvgpu_falcon_sw_init,
+		.falcon_sw_free = nvgpu_falcon_sw_free,
 		.reset = gk20a_falcon_reset,
 		.is_falcon_cpu_halted =  gk20a_is_falcon_cpu_halted,
 		.is_falcon_idle =  gk20a_is_falcon_idle,
@@ -1297,6 +1346,9 @@ static const struct gpu_ops gv11b_ops = {
 		.get_falcon_ctls = gk20a_falcon_get_ctls,
 #endif
 	},
+	.fbp = {
+		.fbp_init_support = nvgpu_fbp_init_support,
+	},
 	.priv_ring = {
 		.enable_priv_ring = gm20b_priv_ring_enable,
 		.isr = gp10b_priv_ring_isr,
@@ -1354,6 +1406,9 @@ int gv11b_init_hal(struct gk20a *g)
 {
 	struct gpu_ops *gops = &g->ops;
 
+	gops->acr = gv11b_ops.acr;
+	gops->bios = gv11b_ops.bios;
+	gops->fbp = gv11b_ops.fbp;
 	gops->ltc = gv11b_ops.ltc;
 #ifdef CONFIG_NVGPU_COMPRESSION
 	gops->cbc = gv11b_ops.cbc;
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 9754c695b..0a1f50f0e 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -185,6 +185,14 @@
 
 #include <nvgpu/ptimer.h>
 #include <nvgpu/error_notifier.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/ce.h>
+#include <nvgpu/pmu.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_pstate.h>
+#endif
+#include <nvgpu/fbp.h>
+#include <nvgpu/therm.h>
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/class.h>
 #include <nvgpu/debugger.h>
@@ -226,10 +234,20 @@ static void tu104_init_gpu_characteristics(struct gk20a *g)
 
 
 static const struct gpu_ops tu104_ops = {
+	.acr = {
+		.acr_init = nvgpu_acr_init,
+		.acr_construct_execute = nvgpu_acr_construct_execute,
+	},
 	.bios = {
+#ifdef CONFIG_NVGPU_DGPU
+		.bios_sw_init = nvgpu_bios_sw_init,
+		.bios_sw_deinit = nvgpu_bios_sw_deinit,
+#endif /* CONFIG_NVGPU_DGPU */
 		.get_aon_secure_scratch_reg = tu104_get_aon_secure_scratch_reg,
 	},
 	.ltc = {
+		.init_ltc_support = nvgpu_init_ltc_support,
+		.ltc_remove_support = nvgpu_ltc_remove_support,
 		.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
 		.init_fs_state = ltc_tu104_init_fs_state,
 		.flush = gm20b_flush_ltc,
@@ -255,6 +273,8 @@ static const struct gpu_ops tu104_ops = {
 	},
 #ifdef CONFIG_NVGPU_COMPRESSION
 	.cbc = {
+		.cbc_init_support = nvgpu_cbc_init_support,
+		.cbc_remove_support = nvgpu_cbc_remove_support,
 		.init = tu104_cbc_init,
 		.get_base_divisor = tu104_cbc_get_base_divisor,
 		.alloc_comptags = tu104_cbc_alloc_comptags,
@@ -263,6 +283,12 @@ static const struct gpu_ops tu104_ops = {
 	},
 #endif
 	.ce = {
+		.ce_init_support = nvgpu_ce_init_support,
+#ifdef CONFIG_NVGPU_DGPU
+		.ce_app_init_support = nvgpu_ce_app_init_support,
+		.ce_app_suspend = nvgpu_ce_app_suspend,
+		.ce_app_destroy = nvgpu_ce_app_destroy,
+#endif
 		.set_pce2lce_mapping = tu104_ce_set_pce2lce_mapping,
 		.isr_stall = gv11b_ce_stall_isr,
 		.isr_nonstall = NULL,
@@ -272,6 +298,10 @@ static const struct gpu_ops tu104_ops = {
 		.init_prod_values = gv11b_ce_init_prod_values,
 	},
 	.gr = {
+		.gr_prepare_sw = nvgpu_gr_prepare_sw,
+		.gr_enable_hw = nvgpu_gr_enable_hw,
+		.gr_init_support = nvgpu_gr_init_support,
+		.gr_suspend = nvgpu_gr_suspend,
 #ifdef CONFIG_NVGPU_DEBUGGER
 		.get_gr_status = gr_gm20b_get_gr_status,
 		.set_alpha_circular_buffer_size =
@@ -333,6 +363,8 @@ static const struct gpu_ops tu104_ops = {
 		.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 		.ecc = {
+			.ecc_init_support = nvgpu_ecc_init_support,
+			.ecc_remove_support = nvgpu_ecc_remove_support,
 			.detect = NULL,
 			.init = tu104_ecc_init,
 		},
@@ -864,6 +896,8 @@ static const struct gpu_ops tu104_ops = {
 			tu104_blcg_hshub_load_gating_prod,
 	},
 	.fifo = {
+		.fifo_init_support = nvgpu_fifo_init_support,
+		.fifo_suspend = nvgpu_fifo_suspend,
 		.init_fifo_setup_hw = tu104_init_fifo_setup_hw,
 		.preempt_channel = gv11b_fifo_preempt_channel,
 		.preempt_tsg = gv11b_fifo_preempt_tsg,
@@ -1084,6 +1118,9 @@ static const struct gpu_ops tu104_ops = {
 		.is_fw_defined = tu104_netlist_is_firmware_defined,
 	},
 	.mm = {
+		.init_mm_support = nvgpu_init_mm_support,
+		.pd_cache_init = nvgpu_pd_cache_init,
+		.mm_suspend = nvgpu_mm_suspend,
 		.vm_bind_channel = nvgpu_vm_bind_channel,
 		.setup_hw = nvgpu_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
@@ -1117,6 +1154,7 @@ static const struct gpu_ops tu104_ops = {
 		}
 	},
 	.therm = {
+		.init_therm_support = nvgpu_init_therm_support,
 		/* PROD values match with H/W INIT values */
 		.init_elcg_mode = gv11b_therm_init_elcg_mode,
 		.init_blcg_mode = gm20b_therm_init_blcg_mode,
@@ -1130,6 +1168,13 @@ static const struct gpu_ops tu104_ops = {
 	},
 #ifdef CONFIG_NVGPU_LS_PMU
 	.pmu = {
+		/* Init */
+		.pmu_early_init = nvgpu_pmu_early_init,
+		.pmu_init = nvgpu_pmu_init,
+		.pmu_pstate_sw_setup = nvgpu_pmu_pstate_sw_setup,
+		.pmu_pstate_pmu_setup = nvgpu_pmu_pstate_pmu_setup,
+		.pmu_destroy = nvgpu_pmu_destroy,
+
 		.falcon_base_addr = tu104_pmu_falcon_base_addr,
 		.pmu_queue_tail = gk20a_pmu_queue_tail,
 		.pmu_get_queue_head = tu104_pmu_queue_head_r,
@@ -1179,6 +1224,7 @@ static const struct gpu_ops tu104_ops = {
 	},
 #ifdef CONFIG_NVGPU_CLK_ARB
 	.clk_arb = {
+		.clk_arb_init_arbiter = nvgpu_clk_arb_init_arbiter,
 		.check_clk_arb_support = gv100_check_clk_arb_support,
 		.get_arbiter_clk_domains = gv100_get_arbiter_clk_domains,
 		.get_arbiter_f_points = gv100_get_arbiter_f_points,
@@ -1312,6 +1358,8 @@ static const struct gpu_ops tu104_ops = {
 		.disable_shadow_rom = NULL,
 	},
 	.falcon = {
+		.falcon_sw_init = nvgpu_falcon_sw_init,
+		.falcon_sw_free = nvgpu_falcon_sw_free,
 		.reset = gk20a_falcon_reset,
 		.is_falcon_cpu_halted =  gk20a_is_falcon_cpu_halted,
 		.is_falcon_idle =  gk20a_is_falcon_idle,
@@ -1335,6 +1383,9 @@ static const struct gpu_ops tu104_ops = {
 		.get_falcon_ctls = gk20a_falcon_get_ctls,
 #endif
 	},
+	.fbp = {
+		.fbp_init_support = nvgpu_fbp_init_support,
+	},
 	.priv_ring = {
 		.enable_priv_ring = gm20b_priv_ring_enable,
 		.isr = gp10b_priv_ring_isr,
@@ -1416,6 +1467,9 @@ static const struct gpu_ops tu104_ops = {
 #endif
 #ifdef CONFIG_NVGPU_DGPU
 	.sec2 = {
+		.init_sec2_setup_sw = nvgpu_init_sec2_setup_sw,
+		.init_sec2_support = nvgpu_init_sec2_support,
+		.sec2_destroy = nvgpu_sec2_destroy,
 		.secured_sec2_start = tu104_start_sec2_secure,
 		.enable_irq = tu104_sec2_enable_irq,
 		.is_interrupted = tu104_sec2_is_interrupted,
@@ -1467,6 +1521,8 @@ int tu104_init_hal(struct gk20a *g)
 	struct gpu_ops *gops = &g->ops;
 
 	gops->bios = tu104_ops.bios;
+	gops->acr = tu104_ops.acr;
+	gops->fbp = tu104_ops.fbp;
 	gops->ltc = tu104_ops.ltc;
 #ifdef CONFIG_NVGPU_COMPRESSION
 	gops->cbc = tu104_ops.cbc;
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
index 02d4fa056..2fe69daa1 100644
--- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
@@ -28,6 +28,15 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/gr/gr_intr.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/ce.h>
+#include <nvgpu/pmu.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_pstate.h>
+#endif
+#include <nvgpu/fbp.h>
+#include <nvgpu/therm.h>
+#include <nvgpu/clk_arb.h>
 
 #include <nvgpu/vgpu/ce_vgpu.h>
 #include <nvgpu/vgpu/vm_vgpu.h>
@@ -106,7 +115,18 @@
 #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
 
 static const struct gpu_ops vgpu_gp10b_ops = {
+	.acr = {
+		.acr_init = nvgpu_acr_init,
+		.acr_construct_execute = nvgpu_acr_construct_execute,
+	},
+#ifdef CONFIG_NVGPU_DGPU
+	.bios = {
+		.bios_sw_init = nvgpu_bios_sw_init,
+	},
+#endif /* CONFIG_NVGPU_DGPU */
 	.ltc = {
+		.init_ltc_support = nvgpu_init_ltc_support,
+		.ltc_remove_support = nvgpu_ltc_remove_support,
 		.determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
 		.init_fs_state = vgpu_ltc_init_fs_state,
 		.flush = NULL,
@@ -130,6 +150,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	},
 #ifdef CONFIG_NVGPU_COMPRESSION
 	.cbc = {
+		.cbc_init_support = nvgpu_cbc_init_support,
+		.cbc_remove_support = nvgpu_cbc_remove_support,
 		.init = NULL,
 		.alloc_comptags = vgpu_cbc_alloc_comptags,
 		.ctrl = NULL,
@@ -137,11 +159,21 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	},
 #endif
 	.ce = {
+		.ce_init_support = nvgpu_ce_init_support,
+#ifdef CONFIG_NVGPU_DGPU
+		.ce_app_init_support = nvgpu_ce_app_init_support,
+		.ce_app_suspend = nvgpu_ce_app_suspend,
+		.ce_app_destroy = nvgpu_ce_app_destroy,
+#endif
 		.isr_stall = NULL,
 		.isr_nonstall = NULL,
 		.get_num_pce = vgpu_ce_get_num_pce,
 	},
 	.gr = {
+		.gr_prepare_sw = nvgpu_gr_prepare_sw,
+		.gr_enable_hw = nvgpu_gr_enable_hw,
+		.gr_init_support = nvgpu_gr_init_support,
+		.gr_suspend = nvgpu_gr_suspend,
 #ifdef CONFIG_NVGPU_DEBUGGER
 		.set_alpha_circular_buffer_size = NULL,
 		.set_circular_buffer_size = NULL,
@@ -433,6 +465,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.pg_gr_load_gating_prod = NULL,
 	},
 	.fifo = {
+		.fifo_init_support = nvgpu_fifo_init_support,
+		.fifo_suspend = nvgpu_fifo_suspend,
 		.init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
 		.preempt_channel = vgpu_fifo_preempt_channel,
 		.preempt_tsg = vgpu_fifo_preempt_tsg,
@@ -598,6 +632,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.is_fw_defined = gp10b_netlist_is_firmware_defined,
 	},
 	.mm = {
+		.init_mm_support = nvgpu_init_mm_support,
+		.pd_cache_init = nvgpu_pd_cache_init,
+		.mm_suspend = nvgpu_mm_suspend,
 		.vm_bind_channel = vgpu_vm_bind_channel,
 		.setup_hw = NULL,
 		.is_bar1_supported = gm20b_mm_is_bar1_supported,
@@ -632,6 +669,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	},
 #endif
 	.therm = {
+		.init_therm_support = nvgpu_init_therm_support,
 		.init_therm_setup_hw = NULL,
 		.init_elcg_mode = NULL,
 		.init_blcg_mode = NULL,
@@ -639,6 +677,11 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	},
 #ifdef CONFIG_NVGPU_LS_PMU
 	.pmu = {
+		.pmu_early_init = nvgpu_pmu_early_init,
+		.pmu_init = nvgpu_pmu_init,
+		.pmu_pstate_sw_setup = nvgpu_pmu_pstate_sw_setup,
+		.pmu_pstate_pmu_setup = nvgpu_pmu_pstate_pmu_setup,
+		.pmu_destroy = nvgpu_pmu_destroy,
 		.pmu_setup_elpg = NULL,
 		.pmu_get_queue_head = NULL,
 		.pmu_get_queue_head_size = NULL,
@@ -669,6 +712,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	},
 #endif
 	.clk_arb = {
+		.clk_arb_init_arbiter = nvgpu_clk_arb_init_arbiter,
 		.check_clk_arb_support = gp10b_check_clk_arb_support,
 		.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
 		.get_arbiter_f_points = gp10b_get_arbiter_f_points,
@@ -769,6 +813,13 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.get_max_buffer_size = vgpu_css_get_buffer_size,
 	},
 #endif
+	.falcon = {
+		.falcon_sw_init = nvgpu_falcon_sw_init,
+		.falcon_sw_free = nvgpu_falcon_sw_free,
+	},
+	.fbp = {
+		.fbp_init_support = nvgpu_fbp_init_support,
+	},
 	.priv_ring = {
 		.enable_priv_ring = NULL,
 		.isr = NULL,
@@ -804,6 +855,9 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
 	struct gpu_ops *gops = &g->ops;
 	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
 
+	gops->acr = vgpu_gp10b_ops.acr;
+	gops->bios = vgpu_gp10b_ops.bios;
+	gops->fbp = vgpu_gp10b_ops.fbp;
 	gops->ltc = vgpu_gp10b_ops.ltc;
 #ifdef CONFIG_NVGPU_COMPRESSION
 	gops->cbc = vgpu_gp10b_ops.cbc;
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
index 9dd7a9478..b6dad7051 100644
--- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
@@ -96,6 +96,15 @@
 #include <nvgpu/gr/gr_intr.h>
 #include <nvgpu/vgpu/vgpu.h>
 #include <nvgpu/error_notifier.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/ce.h>
+#include <nvgpu/pmu.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_pstate.h>
+#endif
+#include <nvgpu/fbp.h>
+#include <nvgpu/therm.h>
+#include <nvgpu/clk_arb.h>
 
 #include "common/vgpu/init/init_vgpu.h"
 #include "common/vgpu/fifo/fifo_vgpu.h"
@@ -153,7 +162,18 @@ static void vgpu_gv11b_init_gpu_characteristics(struct gk20a *g)
 }
 
 static const struct gpu_ops vgpu_gv11b_ops = {
+	.acr = {
+		.acr_init = nvgpu_acr_init,
+		.acr_construct_execute = nvgpu_acr_construct_execute,
+	},
+#ifdef CONFIG_NVGPU_DGPU
+	.bios = {
+		.bios_sw_init = nvgpu_bios_sw_init,
+	},
+#endif /* CONFIG_NVGPU_DGPU */
 	.ltc = {
+		.init_ltc_support = nvgpu_init_ltc_support,
+		.ltc_remove_support = nvgpu_ltc_remove_support,
 		.determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
 		.init_fs_state = vgpu_ltc_init_fs_state,
 		.flush = NULL,
@@ -178,17 +198,29 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	},
 #ifdef CONFIG_NVGPU_COMPRESSION
 	.cbc = {
+		.cbc_init_support = nvgpu_cbc_init_support,
+		.cbc_remove_support = nvgpu_cbc_remove_support,
 		.init = NULL,
 		.ctrl = NULL,
 		.alloc_comptags = vgpu_cbc_alloc_comptags,
 	},
 #endif
 	.ce = {
+		.ce_init_support = nvgpu_ce_init_support,
+#ifdef CONFIG_NVGPU_DGPU
+		.ce_app_init_support = nvgpu_ce_app_init_support,
+		.ce_app_suspend = nvgpu_ce_app_suspend,
+		.ce_app_destroy = nvgpu_ce_app_destroy,
+#endif
 		.isr_stall = NULL,
 		.isr_nonstall = NULL,
 		.get_num_pce = vgpu_ce_get_num_pce,
 	},
 	.gr = {
+		.gr_prepare_sw = nvgpu_gr_prepare_sw,
+		.gr_enable_hw = nvgpu_gr_enable_hw,
+		.gr_init_support = nvgpu_gr_init_support,
+		.gr_suspend = nvgpu_gr_suspend,
 #ifdef CONFIG_NVGPU_DEBUGGER
 		.set_alpha_circular_buffer_size = NULL,
 		.set_circular_buffer_size = NULL,
@@ -544,6 +576,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.pg_gr_load_gating_prod = NULL,
 	},
 	.fifo = {
+		.fifo_init_support = nvgpu_fifo_init_support,
+		.fifo_suspend = nvgpu_fifo_suspend,
 		.init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw,
 		.preempt_channel = vgpu_fifo_preempt_channel,
 		.preempt_tsg = vgpu_fifo_preempt_tsg,
@@ -713,6 +747,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.is_fw_defined = gv11b_netlist_is_firmware_defined,
 	},
 	.mm = {
+		.init_mm_support = nvgpu_init_mm_support,
+		.pd_cache_init = nvgpu_pd_cache_init,
+		.mm_suspend = nvgpu_mm_suspend,
 		.vm_bind_channel = vgpu_vm_bind_channel,
 		.setup_hw = NULL,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
@@ -745,6 +782,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		},
 	},
 	.therm = {
+		.init_therm_support = nvgpu_init_therm_support,
 		.init_therm_setup_hw = NULL,
 		.init_elcg_mode = NULL,
 		.init_blcg_mode = NULL,
@@ -752,6 +790,11 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	},
 #ifdef CONFIG_NVGPU_LS_PMU
 	.pmu = {
+		.pmu_early_init = nvgpu_pmu_early_init,
+		.pmu_init = nvgpu_pmu_init,
+		.pmu_pstate_sw_setup = nvgpu_pmu_pstate_sw_setup,
+		.pmu_pstate_pmu_setup = nvgpu_pmu_pstate_pmu_setup,
+		.pmu_destroy = nvgpu_pmu_destroy,
 		.pmu_setup_elpg = NULL,
 		.pmu_get_queue_head = NULL,
 		.pmu_get_queue_head_size = NULL,
@@ -784,6 +827,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	},
 #endif
 	.clk_arb = {
+		.clk_arb_init_arbiter = nvgpu_clk_arb_init_arbiter,
 		.check_clk_arb_support = gp10b_check_clk_arb_support,
 		.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
 		.get_arbiter_f_points = gp10b_get_arbiter_f_points,
@@ -885,6 +929,13 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.get_max_buffer_size = vgpu_css_get_buffer_size,
 	},
 #endif
+	.falcon = {
+		.falcon_sw_init = nvgpu_falcon_sw_init,
+		.falcon_sw_free = nvgpu_falcon_sw_free,
+	},
+	.fbp = {
+		.fbp_init_support = nvgpu_fbp_init_support,
+	},
 	.priv_ring = {
 		.enable_priv_ring = NULL,
 		.isr = NULL,
@@ -919,6 +970,8 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
 	struct gpu_ops *gops = &g->ops;
 	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
 
+	gops->acr = vgpu_gv11b_ops.acr;
+	gops->fbp = vgpu_gv11b_ops.fbp;
 	gops->ltc = vgpu_gv11b_ops.ltc;
 #ifdef CONFIG_NVGPU_COMPRESSION
 	gops->cbc = vgpu_gv11b_ops.cbc;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index e9e2f5a5f..d8e56a4bd 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -48,6 +48,7 @@
  */
 
 struct gk20a;
+struct nvgpu_acr;
 struct nvgpu_fifo;
 struct nvgpu_channel;
 struct nvgpu_gr;
@@ -239,6 +240,13 @@ enum nvgpu_event_id_type {
 
 struct gpu_ops {
 	struct {
+		int (*acr_init)(struct gk20a *g, struct nvgpu_acr **acr);
+		int (*acr_construct_execute)(struct gk20a *g,
+						struct nvgpu_acr *acr);
+	} acr;
+	struct {
+		int (*init_ltc_support)(struct gk20a *g);
+		void (*ltc_remove_support)(struct gk20a *g);
 		u64 (*determine_L2_size_bytes)(struct gk20a *gk20a);
 		struct nvgpu_hw_err_inject_info_desc * (*get_ltc_err_desc)
 			(struct gk20a *g);
@@ -276,6 +284,8 @@ struct gpu_ops {
 	} ltc;
 #ifdef CONFIG_NVGPU_COMPRESSION
 	struct {
+		int (*cbc_init_support)(struct gk20a *g);
+		void (*cbc_remove_support)(struct gk20a *g);
 		void (*init)(struct gk20a *g, struct nvgpu_cbc *cbc);
 		u64 (*get_base_divisor)(struct gk20a *g);
 		int (*alloc_comptags)(struct gk20a *g,
@@ -286,6 +296,10 @@ struct gpu_ops {
 	} cbc;
 #endif
 	struct {
+		int (*ce_init_support)(struct gk20a *g);
+		int (*ce_app_init_support)(struct gk20a *g);
+		void (*ce_app_suspend)(struct gk20a *g);
+		void (*ce_app_destroy)(struct gk20a *g);
 		void (*set_pce2lce_mapping)(struct gk20a *g);
 		void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base);
 		u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base);
@@ -294,6 +308,10 @@ struct gpu_ops {
 		void (*init_prod_values)(struct gk20a *g);
 	} ce;
 	struct {
+		int (*gr_prepare_sw)(struct gk20a *g);
+		int (*gr_enable_hw)(struct gk20a *g);
+		int (*gr_init_support)(struct gk20a *g);
+		int (*gr_suspend)(struct gk20a *g);
 #ifdef CONFIG_NVGPU_DEBUGGER
 		u32 (*get_gr_status)(struct gk20a *g);
 		void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset);
@@ -422,6 +440,8 @@ struct gpu_ops {
 #endif
 
 		struct {
+			int (*ecc_init_support)(struct gk20a *g);
+			void (*ecc_remove_support)(struct gk20a *g);
 			void (*detect)(struct gk20a *g);
 			int (*init)(struct gk20a *g);
 			struct nvgpu_hw_err_inject_info_desc * (*get_mmu_err_desc)
@@ -1041,6 +1061,8 @@ struct gpu_ops {
 		void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod);
 	} cg;
 	struct {
+		int (*fifo_init_support)(struct gk20a *g);
+		int (*fifo_suspend)(struct gk20a *g);
 		int (*setup_sw)(struct gk20a *g);
 		void (*cleanup_sw)(struct gk20a *g);
 		int (*init_fifo_setup_hw)(struct gk20a *g);
@@ -1330,6 +1352,9 @@ struct gpu_ops {
 		bool (*is_fw_defined)(void);
 	} netlist;
 	struct {
+		int (*pd_cache_init)(struct gk20a *g);
+		int (*init_mm_support)(struct gk20a *g);
+		int (*mm_suspend)(struct gk20a *g);
 		int (*vm_bind_channel)(struct vm_gk20a *vm,
 				struct nvgpu_channel *ch);
 		int (*setup_hw)(struct gk20a *g);
@@ -1408,6 +1433,7 @@ struct gpu_ops {
 	} pramin;
 #endif
 	struct {
+		int (*init_therm_support)(struct gk20a *g);
 		int (*init_therm_setup_hw)(struct gk20a *g);
 		void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
 		void (*init_blcg_mode)(struct gk20a *g, u32 mode, u32 engine);
@@ -1427,6 +1453,12 @@ struct gpu_ops {
 		u32 (*idle_slowdown_disable)(struct gk20a *g);
 	} therm;
 	struct {
+		int (*pmu_early_init)(struct gk20a *g,
+						struct nvgpu_pmu **pmu_p);
+		int (*pmu_init)(struct gk20a *g, struct nvgpu_pmu *pmu);
+		int (*pmu_destroy)(struct gk20a *g, struct nvgpu_pmu *pmu);
+		int (*pmu_pstate_sw_setup)(struct gk20a *g);
+		int (*pmu_pstate_pmu_setup)(struct gk20a *g);
 		struct nvgpu_hw_err_inject_info_desc * (*get_pmu_err_desc)
 			(struct gk20a *g);
 		bool (*is_pmu_supported)(struct gk20a *g);
@@ -1535,6 +1567,7 @@ struct gpu_ops {
 	} clk;
 #ifdef CONFIG_NVGPU_CLK_ARB
 	struct {
+		int (*clk_arb_init_arbiter)(struct gk20a *g);
 		int (*arbiter_clk_init)(struct gk20a *g);
 		bool (*check_clk_arb_support)(struct gk20a *g);
 		u32 (*get_arbiter_clk_domains)(struct gk20a *g);
@@ -1671,6 +1704,10 @@ struct gpu_ops {
 	} ptimer;
 
 	struct {
+		int (*bios_sw_init)(struct gk20a *g,
+					struct nvgpu_bios **bios);
+		void (*bios_sw_deinit)(struct gk20a *g,
+					struct nvgpu_bios *bios);
 		u32 (*get_aon_secure_scratch_reg)(struct gk20a *g, u32 i);
 	} bios;
 
@@ -1713,6 +1750,8 @@ struct gpu_ops {
 	} xve;
 #endif
 	struct {
+		int (*falcon_sw_init)(struct gk20a *g, u32 flcn_id);
+		void (*falcon_sw_free)(struct gk20a *g, u32 flcn_id);
 		void (*reset)(struct nvgpu_falcon *flcn);
 		bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn);
 		bool (*is_falcon_idle)(struct nvgpu_falcon *flcn);
@@ -1748,6 +1787,9 @@ struct gpu_ops {
 					u32 *sctl, u32 *cpuctl);
 #endif
 	} falcon;
+	struct {
+		int (*fbp_init_support)(struct gk20a *g);
+	} fbp;
 	struct {
 		void (*enable_priv_ring)(struct gk20a *g);
 		void (*isr)(struct gk20a *g);
@@ -1880,6 +1922,10 @@ struct gpu_ops {
 						u32 value);
 	} top;
 	struct {
+		int (*init_sec2_setup_sw)(struct gk20a *g,
+						struct nvgpu_sec2 *sec2);
+		int (*init_sec2_support)(struct gk20a *g);
+		int (*sec2_destroy)(struct gk20a *g);
 		void (*secured_sec2_start)(struct gk20a *g);
 		void (*enable_irq)(struct nvgpu_sec2 *sec2, bool enable);
 		bool (*is_interrupted)(struct nvgpu_sec2 *sec2);