diff --git a/drivers/gpu/nvgpu/include/nvgpu/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
index a403c510c..f0296d514 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fuse.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
@@ -21,18 +21,83 @@
  */
 #ifndef NVGPU_FUSE_H
 #define NVGPU_FUSE_H
+/**
+ * @file
+ *
+ * Interface for fuse ops.
+ */
 
 struct gk20a;
 
 #include <nvgpu/types.h>
 
+#ifdef CONFIG_NVGPU_NON_FUSA
 int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g);
+#endif
 
+/**
+ * @brief -  Write Fuse bypass register which controls fuse bypass.
+ *
+ * @param g [in] - GPU super structure.
+ * @param val [in]- 0 : DISABLED, 1 : ENABLED
+ *
+ * - Write 0/1 to control the fuse bypass.
+ *
+ * @return none.
+ */
 void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val);
-void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val);
-void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val);
-void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val);
-int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
-int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val);
 
+/**
+ * @brief - Enable software write access
+ *
+ * @param g [in] - GPU super structure.
+ * @param val [in] - 0 : READWRITE, 1 : READONLY
+ *
+ * - Bit 0 of the register is the write control register. When set to 1,
+ *   it disables writes to chip.
+ *
+ * @return none.
+ */
+void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val);
+
+/**
+ * @brief - Disable TPC0
+ *
+ * @param g [in] - GPU super structure.
+ * @param val [in] - 1 : DISABLED, 0 : ENABLED
+ *
+ * - Write 1/0 to fuse tpc disable register to disable/enable the TPC0.
+ *
+ * @return none.
+ */
+void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val);
+
+/**
+ * @brief - Disable TPC1
+ *
+ * @param g [in] - GPU super structure.
+ * @param val [in] - 1 : DISABLED, 0 : ENABLED
+ *
+ * - Write 1/0 to fuse tpc disable register to disable/enable the TPC1.
+ *
+ * @return none.
+ */
+void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val);
+
+/**
+ * @brief - Reads GCPLEX_CONFIG_FUSE configuration.
+ *
+ * @param g [in] - GPU super structure.
+ * @param val [out] - Populated with register GCPLEX_CONFIG_FUSE value.
+ *
+ * - Provide information about the GPU complex configuration.
+ *
+ * @return 0 on success.
+ *
+ */
+int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
+
+#ifdef CONFIG_NVGPU_NON_FUSA
+int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val);
+#endif
 #endif /* NVGPU_FUSE_H */
diff --git a/drivers/gpu/nvgpu/os/posix/fuse.c b/drivers/gpu/nvgpu/os/posix/fuse.c
index b4b18b672..000591a46 100644
--- a/drivers/gpu/nvgpu/os/posix/fuse.c
+++ b/drivers/gpu/nvgpu/os/posix/fuse.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,10 +26,12 @@
 #include <nvgpu/posix/io.h>
 #include <nvgpu/posix/soc_fuse.h>
 
+#ifdef CONFIG_NVGPU_NON_FUSA
 int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g)
 {
 	return 0;
 }
+#endif
 
 /*
  * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
@@ -91,6 +93,7 @@ int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
 	return p->callbacks->tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
 }
 
+#ifdef CONFIG_NVGPU_NON_FUSA
 int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
 {
 	struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
@@ -101,3 +104,4 @@ int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
 
 	return p->callbacks->tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
 }
+#endif