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gpu: nvgpu: multimedia engine enumeration changes

Browse Source 
- Changes to fetch and expose supported multimedia engines to umd
- Unit and litter defines for multimedia engines
- Add functions to get runlist id

Jira NVGPU-9429
Bug 3962979

Signed-off-by: Santosh BS <santoshb@nvidia.com>
Change-Id: I072b4aac803c4a70d3659857cb0d804755c5dbd7
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2900765
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: V M S Seeta Rama Raju Mudundi <srajum@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Santosh BS
2023-05-09 14:50:01 +05:30
committed by mobile promotions
parent ef1fb41e54
commit 54b01e881b
10 changed files with 220 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
drivers/gpu/nvgpu/common/device.c
View File

@@ -61,15 +61,15 @@ static inline const char *nvgpu_device_type_to_str(const struct nvgpu_device *de
case NVGPU_DEVTYPE_NVENC:
str = "NVENC";
break;
case NVGPU_DEVTYPE_OFA:
str = "OFA";
break;
case NVGPU_DEVTYPE_NVDEC:
str = "NVDEC";
break;
case NVGPU_DEVTYPE_NVJPG:
str = "NVJPG";
break;
case NVGPU_DEVTYPE_NVOFA:
str = "NVOFA";
break;
default:
break;
}
@@ -367,6 +367,13 @@ bool nvgpu_device_is_nvenc(struct gk20a *g, const struct nvgpu_device *dev)
return dev->type == NVGPU_DEVTYPE_NVENC;
}
bool nvgpu_device_is_ofa(struct gk20a *g, const struct nvgpu_device *dev)
{
(void)g;
return dev->type == NVGPU_DEVTYPE_OFA;
}
bool nvgpu_device_is_nvdec(struct gk20a *g, const struct nvgpu_device *dev)
{
(void)g;
@@ -381,9 +388,19 @@ bool nvgpu_device_is_nvjpg(struct gk20a *g, const struct nvgpu_device *dev)
return dev->type == NVGPU_DEVTYPE_NVJPG;
}
bool nvgpu_device_is_nvofa(struct gk20a *g, const struct nvgpu_device *dev)
bool nvgpu_device_is_multimedia(struct gk20a *g, const struct nvgpu_device *dev)
{
u32 dev_type, instance;
s32 mm_engine;
(void)g;
return dev->type == NVGPU_DEVTYPE_NVOFA;
for (mm_engine = NVGPU_MULTIMEDIA_ENGINE_NVENC; mm_engine < NVGPU_MULTIMEDIA_ENGINE_MAX;
mm_engine++) {
if (nvgpu_multimedia_get_devtype(mm_engine, &dev_type, &instance)) {
if (dev->type == dev_type) {
return true;
}
}
}
return false;
}

67
drivers/gpu/nvgpu/common/fifo/engines.c
View File

@@ -44,6 +44,7 @@
#include <nvgpu/fifo.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/swprofile.h>
#include <nvgpu/multimedia.h>
#include <nvgpu/fifo/swprofile.h>
@@ -637,6 +638,42 @@ u32 nvgpu_engine_get_nvenc_runlist_id(struct gk20a *g)
return dev->runlist_id;
}
u32 nvgpu_engine_get_ofa_runlist_id(struct gk20a *g)
{
const struct nvgpu_device *dev;
dev = nvgpu_device_get(g, NVGPU_DEVTYPE_OFA, 0);
if (dev == NULL) {
return NVGPU_INVALID_RUNLIST_ID;
}
return dev->runlist_id;
}
u32 nvgpu_engine_get_nvdec_runlist_id(struct gk20a *g)
{
const struct nvgpu_device *dev;
dev = nvgpu_device_get(g, NVGPU_DEVTYPE_NVDEC, 0);
if (dev == NULL) {
return NVGPU_INVALID_RUNLIST_ID;
}
return dev->runlist_id;
}
u32 nvgpu_engine_get_nvjpg_runlist_id(struct gk20a *g)
{
const struct nvgpu_device *dev;
dev = nvgpu_device_get(g, NVGPU_DEVTYPE_NVJPG, 0);
if (dev == NULL) {
return NVGPU_INVALID_RUNLIST_ID;
}
return dev->runlist_id;
}
bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id)
{
u32 i;
@@ -655,12 +692,17 @@ bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id)
bool nvgpu_engine_is_multimedia_runlist_id(struct gk20a *g, u32 runlist_id)
{
u32 dev_type, instance;
s32 mm_engine;
const struct nvgpu_device *dev;
/* Will be extended for other multimedia engine types */
nvgpu_device_for_each(g, dev, NVGPU_DEVTYPE_NVENC) {
if (dev->runlist_id == runlist_id) {
return true;
for (mm_engine = NVGPU_MULTIMEDIA_ENGINE_NVENC; mm_engine < NVGPU_MULTIMEDIA_ENGINE_MAX;
mm_engine++) {
if (nvgpu_multimedia_get_devtype(mm_engine, &dev_type, &instance)) {
dev = nvgpu_device_get(g, dev_type, instance);
if ((dev != NULL) && (dev->runlist_id == runlist_id)) {
return true;
}
}
}
@@ -886,6 +928,8 @@ int nvgpu_engine_init_info(struct nvgpu_fifo *f)
int err;
struct gk20a *g = f->g;
const struct nvgpu_device *dev;
u32 dev_type, instance;
s32 mm_engine;
f->num_engines = 0;
@@ -900,12 +944,19 @@ int nvgpu_engine_init_info(struct nvgpu_fifo *f)
}
}
nvgpu_device_for_each(g, dev, NVGPU_DEVTYPE_NVENC) {
err = nvgpu_engine_init_one_dev(f, dev);
if (err != 0) {
return err;
for (mm_engine = NVGPU_MULTIMEDIA_ENGINE_NVENC; mm_engine < NVGPU_MULTIMEDIA_ENGINE_MAX;
mm_engine++) {
if (nvgpu_multimedia_get_devtype(mm_engine, &dev_type, &instance)) {
dev = nvgpu_device_get(g, dev_type, instance);
if (dev != NULL) {
err = nvgpu_engine_init_one_dev(f, dev);
if (err != 0) {
return err;
}
}
}
}
err = g->ops.engine.init_ce_info(f);
return err;
}

36
drivers/gpu/nvgpu/common/multimedia/multimedia.c
View File

@@ -35,6 +35,7 @@
#include <nvgpu/multimedia.h>
#include <nvgpu/tsg.h>
#include <nvgpu/channel.h>
#include <nvgpu/device.h>
#include "multimedia_priv.h"
#include "nvenc_bootstrap.h"
@@ -176,7 +177,7 @@ void nvgpu_multimedia_free_ctx(struct gk20a *g, struct nvgpu_multimedia_ctx *eng
void nvgpu_multimedia_free_all_ctx(struct nvgpu_tsg *tsg)
{
enum nvgpu_multimedia_engine eng;
s32 eng;
struct nvgpu_multimedia_ctx *eng_ctx;
struct gk20a *g = tsg->g;
@@ -254,3 +255,36 @@ free_ucode:
nvgpu_release_firmware(g, multimedia_fw);
return err;
}
bool nvgpu_multimedia_get_devtype(s32 multimedia_id, u32 *dev_type, u32 *instance)
{
bool isValid = true;
switch (multimedia_id) {
case NVGPU_MULTIMEDIA_ENGINE_NVENC:
*dev_type = NVGPU_DEVTYPE_NVENC;
*instance = 0;
break;
case NVGPU_MULTIMEDIA_ENGINE_OFA:
*dev_type = NVGPU_DEVTYPE_OFA;
*instance = 0;
break;
case NVGPU_MULTIMEDIA_ENGINE_NVDEC:
*dev_type = NVGPU_DEVTYPE_NVDEC;
*instance = 0;
break;
case NVGPU_MULTIMEDIA_ENGINE_NVJPG:
*dev_type = NVGPU_DEVTYPE_NVJPG;
*instance = 0;
break;
default:
isValid = false;
break;
}
return isValid;
}

20
drivers/gpu/nvgpu/include/nvgpu/device.h
View File

@@ -117,9 +117,9 @@ struct gk20a;
/**
* @ingroup NVGPU_TOP_DEVICE_INFO_DEFINES
*
* Device type for NVOFA engine instances.
* Device type for OFA engine instances.
*/
#define NVGPU_DEVTYPE_NVOFA 22U
#define NVGPU_DEVTYPE_OFA 22U
#define NVGPU_MAX_DEVTYPE 58U
@@ -363,14 +363,24 @@ bool nvgpu_device_is_nvdec(struct gk20a *g, const struct nvgpu_device *dev);
bool nvgpu_device_is_nvjpg(struct gk20a *g, const struct nvgpu_device *dev);
/**
* @brief Return true if dev is a NVOFA engine device.
* @brief Return true if dev is a OFA engine device.
*
* @param g [in] The GPU.
* @param dev [in] A device.
*
* @return true if \a dev matches the NVOFA device type.
* @return true if \a dev matches the OFA device type.
*/
bool nvgpu_device_is_nvofa(struct gk20a *g, const struct nvgpu_device *dev);
bool nvgpu_device_is_ofa(struct gk20a *g, const struct nvgpu_device *dev);
/**
* @brief Return true if dev is a multimedia engine device.
*
* @param g [in] The GPU.
* @param dev [in] A device.
*
* @return true if \a dev matches the multimedia device type.
*/
bool nvgpu_device_is_multimedia(struct gk20a *g, const struct nvgpu_device *dev);
/**
* @brief Get all the copy engine pointers for this chip.

59
drivers/gpu/nvgpu/include/nvgpu/engines.h
View File

@@ -63,8 +63,14 @@ enum nvgpu_fifo_engine {
NVGPU_ENGINE_ASYNC_CE = 2U,
/** NVENC engine enum */
NVGPU_ENGINE_NVENC = 3U,
/** OFA engine enum */
NVGPU_ENGINE_OFA = 4U,
/** NVDEC engine enum */
NVGPU_ENGINE_NVDEC = 5U,
/** NVJPG engine enum */
NVGPU_ENGINE_NVJPG = 6U,
/** Invalid engine enum */
NVGPU_ENGINE_INVAL = 4U,
NVGPU_ENGINE_INVAL = 7U,
};
/**
@@ -292,6 +298,57 @@ u32 nvgpu_engine_get_gr_runlist_id(struct gk20a *g);
* nvenc h/w engine id is NULL.
*/
u32 nvgpu_engine_get_nvenc_runlist_id(struct gk20a *g);
/**
* @brief Get runlist id for the first available #NVGPU_ENGINE_OFA engine enum
* type.
*
* @param g [in] The GPU driver struct.
*
* - Get h/w engine id for the first available #NVGPU_ENGINE_OFA engine enum
* type.
* -- Get #nvgpu_engine_info for the first available ofa engine id.
* -- Get #nvgpu_engine_info.runlist_id for first available ofa engine id.
*
* @return #nvgpu_engine_info.runlist_id for the first available ofa engine id.
* @retval U32_MAX if #NVGPU_ENGINE_OFA engine enum type is not available.
* @retval U32_MAX if pointer to #nvgpu_engine_info for the first available
* ofa h/w engine id is NULL.
*/
u32 nvgpu_engine_get_ofa_runlist_id(struct gk20a *g);
/**
* @brief Get runlist id for the first available #NVGPU_ENGINE_NVDEC engine enum
* type.
*
* @param g [in] The GPU driver struct.
*
* - Get h/w engine id for the first available #NVGPU_ENGINE_NVDEC engine enum
* type.
* -- Get #nvgpu_engine_info for the first available nvdec engine id.
* -- Get #nvgpu_engine_info.runlist_id for first available nvdec engine id.
*
* @return #nvgpu_engine_info.runlist_id for the first available nvdec engine id.
* @retval U32_MAX if #NVGPU_ENGINE_NVDEC engine enum type is not available.
* @retval U32_MAX if pointer to #nvgpu_engine_info for the first available
* nvdec h/w engine id is NULL.
*/
u32 nvgpu_engine_get_nvdec_runlist_id(struct gk20a *g);
/**
* @brief Get runlist id for the first available #NVGPU_ENGINE_NVJPG engine enum
* type.
*
* @param g [in] The GPU driver struct.
*
* - Get h/w engine id for the first available #NVGPU_ENGINE_NVJPG engine enum
* type.
* -- Get #nvgpu_engine_info for the first available nvjpg id.
* -- Get #nvgpu_engine_info.runlist_id for first available nvjpg engine id.
*
* @return #nvgpu_engine_info.runlist_id for the first available nvjpg engine id.
* @retval U32_MAX if #NVGPU_ENGINE_NVJPG engine enum type is not available.
* @retval U32_MAX if pointer to #nvgpu_engine_info for the first available
* nvjpg h/w engine id is NULL.
*/
u32 nvgpu_engine_get_nvjpg_runlist_id(struct gk20a *g);
/**
* @brief Check if runlist id corresponds to runlist id of one of the
* engine ids supported by h/w.

6
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -304,6 +304,12 @@ struct railgate_stats {
#define GPU_LIT_PERFMON_PMMGPC_ROP_DOMAIN_COUNT 57
/** NVENC class. */
#define GPU_LIT_NVENC_CLASS 58
/** OFA class. */
#define GPU_LIT_OFA_CLASS 59
/** NVDEC class. */
#define GPU_LIT_NVDEC_CLASS 60
/** NVJPG class. */
#define GPU_LIT_NVJPG_CLASS 61
/** Macro to get litter values corresponding to the litter defines. */
#define nvgpu_get_litter_value(g, v) ((g)->ops.get_litter_value((g), v))

7
drivers/gpu/nvgpu/include/nvgpu/mc.h
View File

@@ -146,15 +146,18 @@ struct nvgpu_device;
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
#define NVGPU_UNIT_PWR BIT32(4)
#endif
#ifdef CONFIG_NVGPU_DGPU
/** NVDEC unit */
#define NVGPU_UNIT_NVDEC BIT32(5)
#endif
/** CE2 unit */
#define NVGPU_UNIT_CE2 BIT32(6)
/** NVLINK unit */
#define NVGPU_UNIT_NVLINK BIT32(7)
/** NVENC unit */
#define NVGPU_UNIT_NVENC BIT32(8)
/** OFA unit */
#define NVGPU_UNIT_OFA BIT32(9)
/** NVJPG unit */
#define NVGPU_UNIT_NVJPG BIT32(10)
/** Bit offset of the Architecture field in the HW version register */
#define NVGPU_GPU_ARCHITECTURE_SHIFT 4U

13
drivers/gpu/nvgpu/include/nvgpu/multimedia.h
View File

@@ -34,11 +34,17 @@ struct nvgpu_channel;
/**
* Multimedia engine enum types supported from driver.
*/
enum nvgpu_multimedia_engine {
enum {
/** NVENC engine enum */
NVGPU_MULTIMEDIA_ENGINE_NVENC = 0U,
NVGPU_MULTIMEDIA_ENGINE_NVENC = 0U,
/** OFA engine enum */
NVGPU_MULTIMEDIA_ENGINE_OFA = 1U,
/** NVDEC engine enum */
NVGPU_MULTIMEDIA_ENGINE_NVDEC = 2U,
/** NVJPG engine enum */
NVGPU_MULTIMEDIA_ENGINE_NVJPG = 3U,
/** Invalid engine enum */
NVGPU_MULTIMEDIA_ENGINE_MAX
NVGPU_MULTIMEDIA_ENGINE_MAX = 4U
};
/**
@@ -63,4 +69,5 @@ struct nvgpu_multimedia_ctx {
int nvgpu_multimedia_setup_ctx(struct nvgpu_channel *ch, u32 class_num, u32 flags);
void nvgpu_multimedia_free_ctx(struct gk20a *g, struct nvgpu_multimedia_ctx *eng_ctx);
void nvgpu_multimedia_free_all_ctx(struct nvgpu_tsg *tsg);
bool nvgpu_multimedia_get_devtype(s32 multimedia_id, u32 *dev_type, u32 *instance);
#endif

8
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -1259,6 +1259,12 @@ static void nvgpu_gpu_fetch_engine_info_item(struct gk20a *g,
}
} else if (nvgpu_device_is_nvenc(g, dev)) {
dst_info->engine_id = NVGPU_GPU_ENGINE_ID_NVENC;
} else if (nvgpu_device_is_ofa(g, dev)) {
dst_info->engine_id = NVGPU_GPU_ENGINE_ID_OFA;
} else if (nvgpu_device_is_nvdec(g, dev)) {
dst_info->engine_id = NVGPU_GPU_ENGINE_ID_NVDEC;
} else if (nvgpu_device_is_nvjpg(g, dev)) {
dst_info->engine_id = NVGPU_GPU_ENGINE_ID_NVJPG;
}
dst_info->engine_instance = dev_inst_id;
@@ -1285,7 +1291,7 @@ static int nvgpu_gpu_get_engine_info(
const struct nvgpu_device *dev = g->fifo.active_engines[i];
struct nvgpu_gpu_get_engine_info_item dst_info;
if (nvgpu_device_is_nvenc(g, dev)) {
if (nvgpu_device_is_multimedia(g, dev)) {
nvgpu_gpu_fetch_engine_info_item(g, &dst_info, dev,
dev->inst_id, dev->runlist_id);
} else {

3
include/uapi/linux/nvgpu-ctrl.h
View File

@@ -699,6 +699,9 @@ struct nvgpu_gpu_get_engine_info_item {
#define NVGPU_GPU_ENGINE_ID_GR_COPY 1
#define NVGPU_GPU_ENGINE_ID_ASYNC_COPY 2
#define NVGPU_GPU_ENGINE_ID_NVENC 5
#define NVGPU_GPU_ENGINE_ID_OFA 6
#define NVGPU_GPU_ENGINE_ID_NVDEC 7
#define NVGPU_GPU_ENGINE_ID_NVJPG 8
__u32 engine_id;
__u32 engine_instance;