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gpu: nvgpu: unit: improve coverage for engines
Improve branch coverage for the following functions: - nvgpu_engine_get_active_eng_info - nvgpu_engine_get_ids - nvgpu_ce_engine_interrupt_mask - nvgpu_engine_get_gr_runlist_id Add unit tests for the following functions: -_nvgpu_engine_get_fast_ce_runlist_id - nvgpu_engine_is_valid_runlist_id - nvgpu_engine_id_to_mmu_fault_id - nvgpu_engine_mmu_fault_id_to_engine_id - nvgpu_engine_get_mask_on_id - nvgpu_engine_get_id_and_type - nvgpu_engine_find_busy_doing_ctxsw - nvgpu_engine_get_runlist_busy_engines - nvgpu_engine_mmu_fault_id_to_veid - nvgpu_engine_mmu_fault_id_to_eng_id_and_veid - nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id Jira NVGPU-4511 Change-Id: Ib340df17468ff3447e271a86af9a47a067f6ad11 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2262222 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
committed by
Alex Waterman
Alex Waterman
parent
45b99f67b2
commit
55510f266d
@@ -30,6 +30,7 @@
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#include <nvgpu/channel_sync.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/engine_status.h>
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#include <nvgpu/tsg.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/runlist.h>
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@@ -43,7 +44,9 @@
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#include "../nvgpu-fifo-common.h"
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#include "../nvgpu-fifo-gv11b.h"
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#include "nvgpu-engine.h"
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#include "nvgpu-engine-status.h"
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#define ENGINE_UNIT_DEBUG
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#ifdef ENGINE_UNIT_DEBUG
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#undef unit_verbose
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#define unit_verbose unit_info
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@@ -60,13 +63,17 @@ struct unit_ctx {
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u32 branches;
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u32 ce_mask;
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u32 eng_mask;
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u32 id;
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u32 is_tsg;
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};
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struct unit_ctx unit_ctx;
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static struct unit_ctx u;
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static void subtest_setup(u32 branches)
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{
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unit_ctx.branches = branches;
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u.branches = branches;
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/* do NOT clean u.eng_mask */
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}
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#define subtest_pruned test_fifo_subtest_pruned
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@@ -272,8 +279,8 @@ int test_engine_ids(struct unit_module *m,
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u32 n, i;
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u32 engine_id;
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unit_ctx.ce_mask = 0;
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unit_ctx.eng_mask = 0;
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u.ce_mask = 0;
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u.eng_mask = 0;
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unit_assert(nvgpu_engine_check_valid_id(g, U32_MAX) == false,
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goto done);
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@@ -290,24 +297,115 @@ int test_engine_ids(struct unit_module *m,
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unit_assert(nvgpu_engine_check_valid_id(g, engine_id) ==
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true, goto done);
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unit_ctx.eng_mask |= BIT(engine_id);
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u.eng_mask |= BIT(engine_id);
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if (e == NVGPU_ENGINE_ASYNC_CE || e == NVGPU_ENGINE_GRCE) {
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unit_ctx.ce_mask |= BIT(engine_id);
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u.ce_mask |= BIT(engine_id);
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}
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}
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}
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unit_assert(nvgpu_engine_get_ids(g, &engine_id, 1,
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NVGPU_ENGINE_GR) == 1, goto done);
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unit_assert(nvgpu_engine_get_ids(g, &engine_id,
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1, NVGPU_ENGINE_GR) == 1, goto done);
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unit_assert(engine_id == nvgpu_engine_get_gr_id(g), goto done);
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unit_assert(unit_ctx.eng_mask != 0, goto done);
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unit_assert(unit_ctx.ce_mask != 0, goto done);
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unit_assert(u.eng_mask != 0, goto done);
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unit_assert(u.ce_mask != 0, goto done);
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unit_assert(nvgpu_engine_get_ids(g, &engine_id,
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0, NVGPU_ENGINE_GR) == 0, goto done);
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unit_assert(nvgpu_engine_get_ids(g, &engine_id,
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1, NVGPU_ENGINE_GRCE) == 1, goto done);
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ret = UNIT_SUCCESS;
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done:
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return ret;
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}
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int test_engine_is_valid_runlist_id(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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int ret = UNIT_FAIL;
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u32 i;
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u32 engine_id;
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u32 runlist_id = 0;
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struct nvgpu_engine_info *engine_info;
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struct nvgpu_fifo *f = &g->fifo;
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for (i = 0; i < f->num_engines; i++) {
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engine_id = f->active_engines_list[i];
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engine_info = &f->engine_info[engine_id];
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unit_assert(nvgpu_engine_is_valid_runlist_id(g,
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engine_info->runlist_id), goto done);
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}
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unit_assert(!nvgpu_engine_is_valid_runlist_id(NULL,
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runlist_id), goto done);
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unit_assert(!nvgpu_engine_is_valid_runlist_id(g,
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NVGPU_INVALID_RUNLIST_ID), goto done);
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ret = UNIT_SUCCESS;
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done:
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return ret;
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}
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int test_engine_get_fast_ce_runlist_id(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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u32 runlist_id;
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int ret = UNIT_FAIL;
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runlist_id = nvgpu_engine_get_fast_ce_runlist_id(g);
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unit_assert(runlist_id != NVGPU_INVALID_RUNLIST_ID, goto done);
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unit_assert(nvgpu_engine_get_fast_ce_runlist_id(NULL) ==
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NVGPU_INVALID_ENG_ID, goto done);
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ret = UNIT_SUCCESS;
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done:
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return ret;
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}
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int test_engine_get_gr_runlist_id(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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struct nvgpu_fifo *f = &g->fifo;
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struct nvgpu_fifo fifo = g->fifo;
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u32 runlist_id;
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int ret = UNIT_FAIL;
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struct nvgpu_engine_info engine_info[2];
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u32 active_engines_list;
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runlist_id = nvgpu_engine_get_gr_runlist_id(g);
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unit_assert(runlist_id != NVGPU_INVALID_RUNLIST_ID, goto done);
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f->num_engines = 1;
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f->max_engines = 1;
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f->active_engines_list = &active_engines_list;
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active_engines_list = 0;
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f->engine_info = engine_info;
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engine_info[0].engine_id = 0;
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engine_info[0].runlist_id = 1;
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/* NVGPU_ENGINE_GR not found */
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engine_info[0].engine_enum = NVGPU_ENGINE_GRCE;
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runlist_id = nvgpu_engine_get_gr_runlist_id(g);
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unit_assert(runlist_id == NVGPU_INVALID_RUNLIST_ID, goto done);
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/* valid entry */
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engine_info[0].engine_enum = NVGPU_ENGINE_GR;
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runlist_id = nvgpu_engine_get_gr_runlist_id(g);
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unit_assert(runlist_id != NVGPU_INVALID_RUNLIST_ID, goto done);
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ret = UNIT_SUCCESS;
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done:
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g->fifo = fifo;
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return ret;
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}
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int test_engine_get_active_eng_info(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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@@ -316,8 +414,12 @@ int test_engine_get_active_eng_info(struct unit_module *m,
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struct nvgpu_engine_info *info;
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u32 eng_mask = 0;
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struct nvgpu_fifo *f = &g->fifo;
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struct nvgpu_fifo fifo = g->fifo;
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for (engine_id = 0; engine_id < f->max_engines; engine_id++) {
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unit_assert(nvgpu_engine_get_active_eng_info(NULL, 0) == NULL,
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goto done);
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for (engine_id = 0; engine_id <= f->max_engines; engine_id++) {
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unit_verbose(m, "engine_id=%u\n", engine_id);
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info = nvgpu_engine_get_active_eng_info(g, engine_id);
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@@ -330,11 +432,16 @@ int test_engine_get_active_eng_info(struct unit_module *m,
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}
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}
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unit_verbose(m, "eng_mask=%x\n", eng_mask);
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unit_verbose(m, "unit_ctx.eng_mask=%x\n", unit_ctx.eng_mask);
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unit_assert(eng_mask == unit_ctx.eng_mask, goto done);
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unit_verbose(m, "u.eng_mask=%x\n", u.eng_mask);
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unit_assert(eng_mask == u.eng_mask, goto done);
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f->num_engines = 0;
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unit_assert(nvgpu_engine_get_active_eng_info(g, 0) == NULL,
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goto done);
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ret = UNIT_SUCCESS;
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done:
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g->fifo = fifo;
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return ret;
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}
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@@ -343,6 +450,7 @@ int test_engine_enum_from_type(struct unit_module *m,
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{
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int ret = UNIT_FAIL;
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int engine_enum;
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struct gpu_ops gops = g->ops;
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engine_enum = nvgpu_engine_enum_from_type(g,
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top_device_info_type_enum_graphics_v());
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@@ -355,8 +463,20 @@ int test_engine_enum_from_type(struct unit_module *m,
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engine_enum = nvgpu_engine_enum_from_type(g, 0xff);
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unit_assert(engine_enum == NVGPU_ENGINE_INVAL, goto done);
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g->ops.top.is_engine_gr = NULL;
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engine_enum = nvgpu_engine_enum_from_type(g,
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top_device_info_type_enum_graphics_v());
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unit_assert(engine_enum == NVGPU_ENGINE_INVAL, goto done);
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g->ops = gops;
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g->ops.top.is_engine_ce = NULL;
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engine_enum = nvgpu_engine_enum_from_type(g,
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top_device_info_type_enum_graphics_v());
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unit_assert(engine_enum == NVGPU_ENGINE_INVAL, goto done);
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ret = UNIT_SUCCESS;
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done:
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g->ops = gops;
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return ret;
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}
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@@ -364,6 +484,7 @@ int test_engine_interrupt_mask(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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int ret = UNIT_FAIL;
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struct gpu_ops gops = g->ops;
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u32 intr_mask =
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nvgpu_gr_engine_interrupt_mask(g) |
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nvgpu_ce_engine_interrupt_mask(g);
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@@ -372,6 +493,9 @@ int test_engine_interrupt_mask(struct unit_module *m,
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u32 mask;
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u32 engine_id;
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struct nvgpu_fifo *f = &g->fifo;
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struct nvgpu_fifo fifo = g->fifo;
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unit_assert(nvgpu_engine_check_valid_id(NULL, 0) == false, goto done);
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unit_assert(intr_mask != 0U, goto done);
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for (engine_id = 0; engine_id < f->max_engines; engine_id++) {
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@@ -387,23 +511,492 @@ int test_engine_interrupt_mask(struct unit_module *m,
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}
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unit_assert(intr_mask == all_mask, goto done);
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unit_assert(nvgpu_engine_act_interrupt_mask(NULL, 0) == 0, goto done);
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g->ops.ce.isr_stall = NULL;
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unit_assert(nvgpu_ce_engine_interrupt_mask(g) == 0, goto done);
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g->ops = gops;
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g->ops.ce.isr_nonstall = NULL;
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unit_assert(nvgpu_ce_engine_interrupt_mask(g) == 0, goto done);
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ce_reset_mask = nvgpu_engine_get_all_ce_reset_mask(g);
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unit_assert(ce_reset_mask != 0, goto done);;
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unit_assert(ce_reset_mask != 0, goto done);
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unit_assert(nvgpu_engine_get_all_ce_reset_mask(NULL) == 0, goto done);
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f->num_engines = 0;
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unit_assert(nvgpu_engine_check_valid_id(g, 0) == false, goto done);
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ret = UNIT_SUCCESS;
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done:
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g->fifo = fifo;
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g->ops = gops;
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return ret;
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}
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int test_engine_mmu_fault_id(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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struct nvgpu_fifo *f = &g->fifo;
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int ret = UNIT_FAIL;
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struct nvgpu_engine_info *engine_info;
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u32 fault_id;
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u32 engine_id;
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u32 id;
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for (engine_id = 0;
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engine_id <= f->max_engines;
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engine_id++) {
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engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
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unit_assert((engine_info == NULL) ==
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!nvgpu_engine_check_valid_id(g, engine_id), goto done);
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fault_id = nvgpu_engine_id_to_mmu_fault_id(g, engine_id);
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unit_assert((fault_id == NVGPU_INVALID_ENG_ID) ==
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!nvgpu_engine_check_valid_id(g, engine_id), goto done);
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unit_assert(!engine_info ||
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(engine_info->fault_id == fault_id), goto done);
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id = nvgpu_engine_mmu_fault_id_to_engine_id(g, fault_id);
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unit_assert((id == NVGPU_INVALID_ENG_ID) ==
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!nvgpu_engine_check_valid_id(g, engine_id), goto done);
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unit_assert(!engine_info ||
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(engine_info->engine_id == id), goto done);
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}
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ret = UNIT_SUCCESS;
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done:
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return ret;
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}
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int test_engine_mmu_fault_id_veid(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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struct nvgpu_fifo *f = &g->fifo;
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struct nvgpu_fifo fifo = g->fifo;
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int ret = UNIT_FAIL;
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struct nvgpu_engine_info *engine_info;
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u32 fault_id;
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u32 engine_id;
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u32 veid;
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u32 gr_eng_fault_id;
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u32 pbdma_id;
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u32 id;
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u32 n;
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u32 i;
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for (engine_id = 0;
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engine_id <= f->max_engines;
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engine_id++) {
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engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
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unit_assert((engine_info == NULL) ==
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!nvgpu_engine_check_valid_id(g, engine_id), goto done);
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fault_id = nvgpu_engine_id_to_mmu_fault_id(g, engine_id);
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unit_assert((fault_id == NVGPU_INVALID_ENG_ID) ==
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!nvgpu_engine_check_valid_id(g, engine_id), goto done);
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unit_assert(!engine_info ||
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(engine_info->fault_id == fault_id), goto done);
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id = nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(g,
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fault_id, &veid);
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unit_assert(!engine_info || (id == engine_id), goto done);
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}
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/* fault_id in GR MMU fault id range */
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engine_id = nvgpu_engine_get_gr_id(g);
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engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
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unit_assert(engine_info->engine_enum == NVGPU_ENGINE_GR,
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goto done);
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gr_eng_fault_id = engine_info->fault_id;
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for (i = 0; i < f->max_subctx_count; i++) {
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fault_id = gr_eng_fault_id + i;
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veid = nvgpu_engine_mmu_fault_id_to_veid(g,
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fault_id, gr_eng_fault_id);
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unit_assert(veid == i, goto done);
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id = nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(g,
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fault_id, &veid);
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unit_assert(veid == i, goto done);
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unit_assert(id == engine_id, goto done);
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nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id(g,
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fault_id, &id, &veid, &pbdma_id);
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unit_assert(id == engine_id, goto done);
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unit_assert(pbdma_id == INVAL_ID, goto done);
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}
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/* fault_id in CE range */
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n = nvgpu_engine_get_ids(g, &engine_id, 1, NVGPU_ENGINE_ASYNC_CE);
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unit_assert(n == 1, goto done);
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engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
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unit_assert(engine_info != NULL, goto done);
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veid = 0xcafe;
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fault_id = engine_info->fault_id;
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id = nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(g,
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fault_id, &veid);
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unit_assert(id == engine_id, goto done);
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unit_assert(veid == INVAL_ID, goto done);
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/* valid CE MMU fault id */
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fault_id = engine_info->fault_id;
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nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id(g,
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fault_id, &id, &veid, &pbdma_id);
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unit_assert(id == engine_id, goto done);
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unit_assert(veid == INVAL_ID, goto done);
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unit_assert(pbdma_id == INVAL_ID, goto done);
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/* valid PBDMA MMU fault id */
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fault_id = 33;
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nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id(g,
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fault_id, &id, &veid, &pbdma_id);
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unit_assert(id == NVGPU_INVALID_ENG_ID, goto done);
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unit_assert(veid == INVAL_ID, goto done);
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unit_assert(pbdma_id != INVAL_ID, goto done);
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/* invalid engine and pbdma MMU fault id */
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pbdma_id = 0xcafe;
|
||||
nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id(g,
|
||||
INVAL_ID, &id, &veid, &pbdma_id);
|
||||
unit_assert(id == NVGPU_INVALID_ENG_ID, goto done);
|
||||
unit_assert(veid == INVAL_ID, goto done);
|
||||
unit_assert(pbdma_id == INVAL_ID, goto done);
|
||||
|
||||
ret = UNIT_SUCCESS;
|
||||
done:
|
||||
g->fifo = fifo;
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define F_GET_MASK_IS_TSG BIT(0)
|
||||
#define F_GET_MASK_LOAD BIT(1)
|
||||
#define F_GET_MASK_BUSY BIT(2)
|
||||
#define F_GET_MASK_SAME_ID BIT(3)
|
||||
#define F_GET_MASK_SAME_TYPE BIT(4)
|
||||
#define F_GET_MASK_LAST BIT(5)
|
||||
|
||||
#define FECS_METHOD_WFI_RESTORE 0x80000U
|
||||
|
||||
static void stub_engine_read_engine_status_info(struct gk20a *g,
|
||||
u32 engine_id, struct nvgpu_engine_status_info *status)
|
||||
{
|
||||
status->ctxsw_status = u.branches & F_GET_MASK_LOAD ?
|
||||
NVGPU_CTX_STATUS_CTXSW_LOAD :
|
||||
NVGPU_CTX_STATUS_VALID;
|
||||
|
||||
status->is_busy = ((u.branches & F_GET_MASK_BUSY) != 0);
|
||||
|
||||
status->ctx_id_type = ENGINE_STATUS_CTX_ID_TYPE_INVALID;
|
||||
status->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID;
|
||||
|
||||
if (u.branches & F_GET_MASK_SAME_TYPE) {
|
||||
status->ctx_id_type =
|
||||
u.branches & F_GET_MASK_IS_TSG ?
|
||||
ENGINE_STATUS_CTX_ID_TYPE_TSGID :
|
||||
ENGINE_STATUS_CTX_ID_TYPE_CHID;
|
||||
status->ctx_next_id_type =
|
||||
u.branches & F_GET_MASK_IS_TSG ?
|
||||
ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID :
|
||||
ENGINE_STATUS_CTX_NEXT_ID_TYPE_CHID;
|
||||
}
|
||||
|
||||
if (u.branches & F_GET_MASK_SAME_ID) {
|
||||
status->ctx_id = u.id;
|
||||
status->ctx_next_id = u.id;
|
||||
} else {
|
||||
status->ctx_id = ~0;
|
||||
status->ctx_next_id = ~0;
|
||||
}
|
||||
}
|
||||
|
||||
int test_engine_get_mask_on_id(struct unit_module *m,
|
||||
struct gk20a *g, void *args)
|
||||
{
|
||||
struct gpu_ops gops = g->ops;
|
||||
int ret = UNIT_FAIL;
|
||||
u32 mask;
|
||||
u32 branches;
|
||||
u32 engine_id = nvgpu_engine_get_gr_id(g);
|
||||
const char *labels[] = {
|
||||
"is_tsg",
|
||||
"load",
|
||||
"busy",
|
||||
"same_id",
|
||||
"same_type"
|
||||
};
|
||||
|
||||
g->ops.engine_status.read_engine_status_info =
|
||||
stub_engine_read_engine_status_info;
|
||||
|
||||
u.id = 0x0100;
|
||||
|
||||
for (branches = 0U; branches < F_GET_MASK_LAST; branches++) {
|
||||
|
||||
u32 id;
|
||||
u32 type;
|
||||
u32 expected_type;
|
||||
|
||||
subtest_setup(branches);
|
||||
unit_verbose(m, "%s branches=%s\n", __func__,
|
||||
branches_str(branches, labels));
|
||||
|
||||
u.is_tsg = ((branches & F_GET_MASK_IS_TSG) != 0);
|
||||
u.id++;
|
||||
|
||||
expected_type = ENGINE_STATUS_CTX_ID_TYPE_INVALID;
|
||||
if (branches & F_GET_MASK_SAME_TYPE) {
|
||||
expected_type = branches & F_GET_MASK_IS_TSG ?
|
||||
ENGINE_STATUS_CTX_ID_TYPE_TSGID :
|
||||
ENGINE_STATUS_CTX_ID_TYPE_CHID;
|
||||
}
|
||||
nvgpu_engine_get_id_and_type(g, engine_id, &id, &type);
|
||||
unit_assert((id == u.id) ==
|
||||
((branches & F_GET_MASK_SAME_ID) != 0), goto done);
|
||||
unit_assert(type == expected_type, goto done);
|
||||
|
||||
mask = nvgpu_engine_get_mask_on_id(g, u.id, u.is_tsg);
|
||||
|
||||
if ((branches & F_GET_MASK_BUSY) &&
|
||||
(branches & F_GET_MASK_SAME_ID) &&
|
||||
(branches & F_GET_MASK_SAME_TYPE)) {
|
||||
unit_assert(mask = u.eng_mask, goto done);
|
||||
} else {
|
||||
unit_assert(mask == 0, goto done);
|
||||
}
|
||||
}
|
||||
|
||||
ret = UNIT_SUCCESS;
|
||||
done:
|
||||
if (ret != UNIT_SUCCESS) {
|
||||
unit_err(m, "%s branches=%s\n", __func__,
|
||||
branches_str(branches, labels));
|
||||
}
|
||||
g->ops = gops;
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define F_FIND_BUSY_CTXSW_IDLE BIT(0)
|
||||
#define F_FIND_BUSY_CTXSW_LOAD BIT(1)
|
||||
#define F_FIND_BUSY_CTXSW_SWITCH_FECS_WFI_RESTORE BIT(2)
|
||||
#define F_FIND_BUSY_CTXSW_SWITCH_FECS_OTHER BIT(3)
|
||||
#define F_FIND_BUSY_CTXSW_SAVE BIT(4)
|
||||
#define F_FIND_BUSY_CTXSW_LAST BIT(5)
|
||||
|
||||
static u32 stub_gr_falcon_read_fecs_ctxsw_mailbox(struct gk20a *g,
|
||||
u32 reg_index)
|
||||
{
|
||||
if (u.branches & F_FIND_BUSY_CTXSW_SWITCH_FECS_WFI_RESTORE) {
|
||||
return FECS_METHOD_WFI_RESTORE;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stub_engine_read_engine_status_info2(struct gk20a *g,
|
||||
u32 engine_id, struct nvgpu_engine_status_info *status)
|
||||
{
|
||||
status->is_busy = ((u.branches & F_FIND_BUSY_CTXSW_IDLE) == 0);
|
||||
|
||||
status->ctx_id = ENGINE_STATUS_CTX_ID_INVALID;
|
||||
status->ctx_id_type = ENGINE_STATUS_CTX_ID_TYPE_INVALID;
|
||||
|
||||
status->ctx_next_id = ENGINE_STATUS_CTX_NEXT_ID_INVALID;
|
||||
status->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID;
|
||||
|
||||
status->ctxsw_status = NVGPU_CTX_STATUS_VALID;
|
||||
|
||||
if (u.branches & F_FIND_BUSY_CTXSW_LOAD) {
|
||||
status->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_LOAD;
|
||||
status->ctx_next_id = u.id;
|
||||
status->ctx_next_id_type = ENGINE_STATUS_CTX_ID_TYPE_TSGID;
|
||||
}
|
||||
|
||||
if (u.branches & F_FIND_BUSY_CTXSW_SWITCH_FECS_WFI_RESTORE) {
|
||||
status->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_SWITCH;
|
||||
status->ctx_next_id = u.id;
|
||||
status->ctx_next_id_type = ENGINE_STATUS_CTX_ID_TYPE_TSGID;
|
||||
}
|
||||
|
||||
if (u.branches & F_FIND_BUSY_CTXSW_SWITCH_FECS_OTHER) {
|
||||
status->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_SWITCH;
|
||||
status->ctx_id = u.id;
|
||||
status->ctx_id_type = ENGINE_STATUS_CTX_ID_TYPE_TSGID;
|
||||
}
|
||||
|
||||
if (u.branches & F_FIND_BUSY_CTXSW_SAVE) {
|
||||
status->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_SAVE;
|
||||
status->ctx_id = u.id;
|
||||
status->ctx_id_type = ENGINE_STATUS_CTX_ID_TYPE_TSGID;
|
||||
}
|
||||
}
|
||||
|
||||
int test_engine_find_busy_doing_ctxsw(struct unit_module *m,
|
||||
struct gk20a *g, void *args)
|
||||
{
|
||||
struct gpu_ops gops = g->ops;
|
||||
struct nvgpu_fifo fifo = g->fifo;
|
||||
struct nvgpu_fifo *f = &g->fifo;
|
||||
int ret = UNIT_FAIL;
|
||||
u32 branches;
|
||||
u32 engine_id;
|
||||
const char *labels[] = {
|
||||
"idle",
|
||||
"load",
|
||||
"switch_fecs_restore",
|
||||
"switch_fecs_other",
|
||||
"save",
|
||||
};
|
||||
|
||||
g->ops.gr.falcon.read_fecs_ctxsw_mailbox =
|
||||
stub_gr_falcon_read_fecs_ctxsw_mailbox;
|
||||
g->ops.engine_status.read_engine_status_info =
|
||||
stub_engine_read_engine_status_info2;
|
||||
f->num_engines = 1;
|
||||
|
||||
u.id = 0x0100;
|
||||
|
||||
for (branches = 0U; branches < F_FIND_BUSY_CTXSW_LAST; branches++) {
|
||||
|
||||
u32 id;
|
||||
bool is_tsg;
|
||||
u32 count;
|
||||
|
||||
count = __builtin_popcount(branches &
|
||||
(F_FIND_BUSY_CTXSW_LOAD |
|
||||
F_FIND_BUSY_CTXSW_SWITCH_FECS_WFI_RESTORE |
|
||||
F_FIND_BUSY_CTXSW_SWITCH_FECS_OTHER |
|
||||
F_FIND_BUSY_CTXSW_SAVE));
|
||||
if (count > 1) {
|
||||
goto pruned;
|
||||
}
|
||||
|
||||
if ((branches & F_FIND_BUSY_CTXSW_IDLE) &&
|
||||
(branches & ~F_FIND_BUSY_CTXSW_IDLE)) {
|
||||
pruned:
|
||||
unit_verbose(m, "%s branches=%s (pruned)\n",
|
||||
__func__, branches_str(branches, labels));
|
||||
continue;
|
||||
}
|
||||
|
||||
subtest_setup(branches);
|
||||
unit_verbose(m, "%s branches=%s\n", __func__,
|
||||
branches_str(branches, labels));
|
||||
|
||||
u.id++;
|
||||
|
||||
is_tsg = false;
|
||||
engine_id = nvgpu_engine_find_busy_doing_ctxsw(g, &id, &is_tsg);
|
||||
|
||||
if ((branches & F_FIND_BUSY_CTXSW_IDLE) || (count == 0)) {
|
||||
unit_assert(engine_id == NVGPU_INVALID_ENG_ID,
|
||||
goto done);
|
||||
unit_assert(id == NVGPU_INVALID_TSG_ID, goto done);
|
||||
unit_assert(!is_tsg, goto done);
|
||||
} else {
|
||||
unit_assert(engine_id != NVGPU_INVALID_ENG_ID,
|
||||
goto done);
|
||||
unit_assert(id == u.id, goto done);
|
||||
unit_assert(is_tsg, goto done);
|
||||
}
|
||||
}
|
||||
|
||||
ret = UNIT_SUCCESS;
|
||||
done:
|
||||
if (ret != UNIT_SUCCESS) {
|
||||
unit_err(m, "%s branches=%s\n", __func__,
|
||||
branches_str(branches, labels));
|
||||
}
|
||||
g->ops = gops;
|
||||
g->fifo = fifo;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void stub_engine_read_engine_status_info_busy(struct gk20a *g,
|
||||
u32 engine_id, struct nvgpu_engine_status_info *status)
|
||||
{
|
||||
status->is_busy = true;
|
||||
}
|
||||
|
||||
static void stub_engine_read_engine_status_info_idle(struct gk20a *g,
|
||||
u32 engine_id, struct nvgpu_engine_status_info *status)
|
||||
{
|
||||
status->is_busy = false;
|
||||
}
|
||||
|
||||
int test_engine_get_runlist_busy_engines(struct unit_module *m,
|
||||
struct gk20a *g, void *args)
|
||||
{
|
||||
struct gpu_ops gops = g->ops;
|
||||
struct nvgpu_fifo fifo = g->fifo;
|
||||
struct nvgpu_fifo *f = &g->fifo;
|
||||
int ret = UNIT_FAIL;
|
||||
struct nvgpu_engine_info engine_info;
|
||||
u32 engine_id = 0;
|
||||
u32 eng_mask;
|
||||
|
||||
f->num_engines = 1;
|
||||
f->engine_info = &engine_info;
|
||||
f->active_engines_list = &engine_id;
|
||||
engine_info.engine_id = 1;
|
||||
engine_info.runlist_id = 3;
|
||||
g->ops.engine_status.read_engine_status_info =
|
||||
stub_engine_read_engine_status_info_busy;
|
||||
|
||||
/* busy and same runlist_id (match found) */
|
||||
eng_mask = nvgpu_engine_get_runlist_busy_engines(g,
|
||||
engine_info.runlist_id);
|
||||
unit_assert(eng_mask == BIT32(engine_id), goto done);
|
||||
|
||||
/* no entry with matching runlist_id */
|
||||
eng_mask = nvgpu_engine_get_runlist_busy_engines(g, 1);
|
||||
unit_assert(eng_mask == 0, goto done);
|
||||
|
||||
/* no busy entry found */
|
||||
g->ops.engine_status.read_engine_status_info =
|
||||
stub_engine_read_engine_status_info_idle;
|
||||
eng_mask = nvgpu_engine_get_runlist_busy_engines(g,
|
||||
engine_info.runlist_id);
|
||||
unit_assert(eng_mask == 0, goto done);
|
||||
|
||||
/* no entry at all */
|
||||
f->num_engines = 0;
|
||||
eng_mask = nvgpu_engine_get_runlist_busy_engines(g,
|
||||
engine_info.runlist_id);
|
||||
unit_assert(eng_mask == 0, goto done);
|
||||
|
||||
ret = UNIT_SUCCESS;
|
||||
done:
|
||||
g->ops = gops;
|
||||
g->fifo = fifo;
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct unit_module_test nvgpu_engine_tests[] = {
|
||||
UNIT_TEST(setup_sw, test_engine_setup_sw, &unit_ctx, 0),
|
||||
UNIT_TEST(init_support, test_fifo_init_support, &unit_ctx, 0),
|
||||
UNIT_TEST(init_info, test_engine_init_info, &unit_ctx, 0),
|
||||
UNIT_TEST(ids, test_engine_ids, &unit_ctx, 0),
|
||||
UNIT_TEST(get_active_eng_info, test_engine_get_active_eng_info, &unit_ctx, 0),
|
||||
UNIT_TEST(enum_from_type, test_engine_enum_from_type, &unit_ctx, 0),
|
||||
UNIT_TEST(interrupt_mask, test_engine_interrupt_mask, &unit_ctx, 0),
|
||||
UNIT_TEST(remove_support, test_fifo_remove_support, &unit_ctx, 0),
|
||||
UNIT_TEST(setup_sw, test_engine_setup_sw, &u, 0),
|
||||
UNIT_TEST(init_support, test_fifo_init_support, &u, 0),
|
||||
UNIT_TEST(init_info, test_engine_init_info, &u, 0),
|
||||
UNIT_TEST(ids, test_engine_ids, &u, 0),
|
||||
UNIT_TEST(get_active_eng_info, test_engine_get_active_eng_info, &u, 0),
|
||||
UNIT_TEST(enum_from_type, test_engine_enum_from_type, &u, 0),
|
||||
UNIT_TEST(interrupt_mask, test_engine_interrupt_mask, &u, 0),
|
||||
UNIT_TEST(get_fast_ce_runlist_id,
|
||||
test_engine_get_fast_ce_runlist_id, &u, 0),
|
||||
UNIT_TEST(get_gr_runlist_id,
|
||||
test_engine_get_gr_runlist_id, &u, 0),
|
||||
UNIT_TEST(is_valid_runlist_id,
|
||||
test_engine_is_valid_runlist_id, &u, 0),
|
||||
UNIT_TEST(mmu_fault_id, test_engine_mmu_fault_id, &u, 0),
|
||||
UNIT_TEST(mmu_fault_id_veid, test_engine_mmu_fault_id_veid, &u, 0),
|
||||
UNIT_TEST(get_mask_on_id, test_engine_get_mask_on_id, &u, 0),
|
||||
UNIT_TEST(status, test_engine_status, &u, 0),
|
||||
UNIT_TEST(find_busy_doing_ctxsw,
|
||||
test_engine_find_busy_doing_ctxsw, &u, 0),
|
||||
UNIT_TEST(get_runlist_busy_engines,
|
||||
test_engine_get_runlist_busy_engines, &u, 0),
|
||||
UNIT_TEST(remove_support, test_fifo_remove_support, &u, 0),
|
||||
};
|
||||
|
||||
UNIT_MODULE(nvgpu_engine, nvgpu_engine_tests, UNIT_PRIO_NVGPU_TEST);
|
||||
|
||||
Reference in New Issue
Block a user