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gpu: nvgpu: add support for removing comptags and cbc from safety build

Browse Source 
Safety build does not support compression. This patch adds support to
compile out compression related changes - comptags, cbc.

JIRA NVGPU-3532

Change-Id: I20e4ca7df46ceec175b903a6a62dff141140e787
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125473
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-05-23 10:19:22 +05:30
committed by mobile promotions
parent 840972c1cc
commit 556ddaf9a3
41 changed files with 272 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/Kconfig
View File

@@ -174,3 +174,10 @@ config NVGPU_LS_PMU
default y
help
Support for iGPU LS PMU enable/disable
config NVGPU_COMPRESSION
bool "Compression support"
depends on GK20A
default y
help
Support for compression

20
drivers/gpu/nvgpu/Makefile
View File

@@ -39,6 +39,7 @@ ccflags-y += -DCONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
ccflags-y += -DCONFIG_NVGPU_CHANNEL_TSG_CONTROL
ccflags-y += -DCONFIG_NVGPU_POWER_PG
ccflags-y += -DCONFIG_NVGPU_CE
ccflags-y += -DCONFIG_NVGPU_COMPRESSION
obj-$(CONFIG_GK20A) := nvgpu.o
@@ -64,7 +65,6 @@ nvgpu-y += \
common/regops/regops.o \
common/ltc/ltc.o \
common/fbp/fbp.o \
common/cbc/cbc.o \
common/gr/gr_utils.o \
common/gr/gr.o \
common/gr/gr_intr.o \
@@ -242,10 +242,6 @@ nvgpu-y += \
hal/power_features/cg/gv100_gating_reglist.o \
hal/power_features/cg/gv11b_gating_reglist.o \
hal/power_features/cg/tu104_gating_reglist.o \
hal/cbc/cbc_gm20b.o \
hal/cbc/cbc_gp10b.o \
hal/cbc/cbc_gv11b.o \
hal/cbc/cbc_tu104.o \
hal/ptimer/ptimer_gk20a.o \
hal/regops/regops_gm20b.o \
hal/regops/regops_gp10b.o \
@@ -400,7 +396,6 @@ nvgpu-y += \
os/linux/linux-io.o \
os/linux/io_usermode.o \
os/linux/rwsem.o \
os/linux/comptags.o \
os/linux/dmabuf.o \
os/linux/sched.o \
os/linux/linux-channel.o \
@@ -528,7 +523,6 @@ nvgpu-y += \
common/mm/vm_area.o \
common/mm/nvgpu_mem.o \
common/mm/nvgpu_sgt.o \
common/mm/comptags.o \
common/mm/mm.o \
common/mm/dma.o \
common/pramin.o \
@@ -585,7 +579,6 @@ nvgpu-y += \
nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
common/vgpu/ltc/ltc_vgpu.o \
common/vgpu/cbc/cbc_vgpu.o \
common/vgpu/fbp/fbp_vgpu.o \
common/vgpu/gr/gr_vgpu.o \
common/vgpu/gr/ctx_vgpu.o \
@@ -621,4 +614,15 @@ nvgpu-$(CONFIG_NVGPU_CYCLESTATS) += \
ifeq ($(CONFIG_TEGRA_GR_VIRTUALIZATION),y)
nvgpu-$(CONFIG_NVGPU_CYCLESTATS) += \
common/vgpu/perf/cyclestats_snapshot_vgpu.o
nvgpu-$(CONFIG_NVGPU_COMPRESSION) += \
common/vgpu/cbc/cbc_vgpu.o
endif
nvgpu-$(CONFIG_NVGPU_COMPRESSION) += \
os/linux/comptags.o \
common/mm/comptags.o \
common/cbc/cbc.o \
hal/cbc/cbc_gm20b.o \
hal/cbc/cbc_gp10b.o \
hal/cbc/cbc_gv11b.o \
hal/cbc/cbc_tu104.o \

4
drivers/gpu/nvgpu/Makefile.shared.configs
View File

@@ -87,6 +87,10 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
CONFIG_NVGPU_CHANNEL_TSG_CONTROL := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_CHANNEL_TSG_CONTROL
# Enable compression support for safety build for now. To be removed.
CONFIG_NVGPU_COMPRESSION := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_COMPRESSION
#
# Flags enabled for only the regular build profile.
#

28
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -29,7 +29,6 @@ srcs += os/posix/nvgpu.c \
os/posix/posix-nvgpu_mem.c \
os/posix/posix-dma.c \
os/posix/posix-vm.c \
os/posix/posix-comptags.c \
os/posix/firmware.c \
os/posix/soc.c \
os/posix/error_notifier.c \
@@ -48,6 +47,10 @@ srcs += os/posix/nvgpu.c \
ifdef CONFIG_NVGPU_NVLINK
srcs += os/posix/posix-nvlink.c
endif
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += os/posix/posix-comptags.c
endif
endif
# POSIX sources shared between the POSIX and QNX builds.
@@ -82,7 +85,6 @@ srcs += common/utils/enabled.c \
common/mm/vm_area.c \
common/mm/nvgpu_mem.c \
common/mm/nvgpu_sgt.c \
common/mm/comptags.c \
common/mm/mm.c \
common/mm/dma.c \
common/mm/vidmem.c \
@@ -90,7 +92,6 @@ srcs += common/utils/enabled.c \
common/therm/therm.c \
common/pramin.c \
common/ltc/ltc.c \
common/cbc/cbc.c \
common/fbp/fbp.c \
common/io/io.c \
common/ecc.c \
@@ -190,9 +191,6 @@ srcs += common/utils/enabled.c \
hal/power_features/cg/gp10b_gating_reglist.c \
hal/power_features/cg/gv11b_gating_reglist.c \
hal/power_features/cg/gp106_gating_reglist.c \
hal/cbc/cbc_gm20b.c \
hal/cbc/cbc_gp10b.c \
hal/cbc/cbc_gv11b.c \
hal/ptimer/ptimer_gk20a.c \
hal/ce/ce2_gk20a.c \
hal/ce/ce_gp10b.c \
@@ -445,13 +443,24 @@ srcs += common/vgpu/init/init_vgpu.c \
common/vgpu/clk_vgpu.c \
common/vgpu/debugger_vgpu.c \
common/vgpu/ltc/ltc_vgpu.c \
common/vgpu/cbc/cbc_vgpu.c \
common/vgpu/fbp/fbp_vgpu.c \
common/vgpu/ce_vgpu.c \
common/vgpu/gv11b/vgpu_gv11b.c \
common/vgpu/gv11b/vgpu_hal_gv11b.c \
common/vgpu/gv11b/vgpu_tsg_gv11b.c \
common/vgpu/gp10b/vgpu_hal_gp10b.c
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += common/vgpu/cbc/cbc_vgpu.c
endif
endif
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += common/mm/comptags.c \
common/cbc/cbc.c \
hal/cbc/cbc_gm20b.c \
hal/cbc/cbc_gp10b.c \
hal/cbc/cbc_gv11b.c
endif
ifeq ($(CONFIG_NVGPU_NVLINK),1)
@@ -503,7 +512,6 @@ srcs += common/sec2/sec2.c \
hal/init/hal_tu104_litter.c \
hal/power_features/cg/gv100_gating_reglist.c \
hal/power_features/cg/tu104_gating_reglist.c \
hal/cbc/cbc_tu104.c \
hal/ltc/ltc_tu104.c \
hal/fb/fb_gv100.c \
hal/fb/fb_tu104.c \
@@ -532,4 +540,8 @@ srcs += common/sec2/sec2.c \
hal/pramin/pramin_tu104.c \
hal/bios/bios_tu104.c \
hal/top/top_gv100.c
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += hal/cbc/cbc_tu104.c
endif
endif

4
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -464,11 +464,13 @@ int gk20a_finalize_poweron(struct gk20a *g)
goto done;
}
#ifdef CONFIG_NVGPU_COMPRESSION
err = nvgpu_cbc_init_support(g);
if (err != 0) {
nvgpu_err(g, "failed to init cbc");
goto done;
}
#endif
g->ops.chip_init_gpu_characteristics(g);
@@ -656,7 +658,9 @@ static void gk20a_free_cb(struct nvgpu_ref *refcount)
nvgpu_ce_destroy(g);
#endif
#ifdef CONFIG_NVGPU_COMPRESSION
nvgpu_cbc_remove_support(g);
#endif
nvgpu_ecc_remove_support(g);

9
drivers/gpu/nvgpu/common/mm/gmmu/page_table.c
View File

@@ -814,11 +814,9 @@ u64 nvgpu_gmmu_map_locked(struct vm_gk20a *vm,
struct gk20a *g = gk20a_from_vm(vm);
int err = 0;
bool allocated = false;
u64 ctag_granularity = g->ops.fb.compression_page_size(g);
struct nvgpu_gmmu_attrs attrs = {
.pgsz = pgsz_idx,
.kind_v = kind_v,
.ctag = (u64)ctag_offset * ctag_granularity,
.cacheable = ((flags & NVGPU_VM_MAP_CACHEABLE) != 0U),
.rw_flag = rw_flag,
.sparse = sparse,
@@ -827,6 +825,10 @@ u64 nvgpu_gmmu_map_locked(struct vm_gk20a *vm,
.aperture = aperture,
.platform_atomic = (flags & NVGPU_VM_MAP_PLATFORM_ATOMIC) != 0U
};
#ifdef CONFIG_NVGPU_COMPRESSION
u64 ctag_granularity = g->ops.fb.compression_page_size(g);
attrs.ctag = (u64)ctag_offset * ctag_granularity;
/*
* We need to add the buffer_offset within compression_page_size so that
@@ -838,6 +840,7 @@ u64 nvgpu_gmmu_map_locked(struct vm_gk20a *vm,
attrs.ctag = nvgpu_safe_add_u64(attrs.ctag,
buffer_offset & (ctag_granularity - U64(1)));
}
#endif
attrs.l3_alloc = (bool)(flags & NVGPU_VM_MAP_L3_ALLOC);
@@ -897,7 +900,9 @@ void nvgpu_gmmu_unmap_locked(struct vm_gk20a *vm,
struct nvgpu_gmmu_attrs attrs = {
.pgsz = pgsz_idx,
.kind_v = 0,
#ifdef CONFIG_NVGPU_COMPRESSION
.ctag = 0,
#endif
.cacheable = false,
.rw_flag = rw_flag,
.sparse = sparse,

4
drivers/gpu/nvgpu/common/mm/mm.c
View File

@@ -43,7 +43,9 @@ int nvgpu_mm_suspend(struct gk20a *g)
nvgpu_vidmem_thread_pause_sync(&g->mm);
#ifdef CONFIG_NVGPU_COMPRESSION
g->ops.mm.cache.cbc_clean(g);
#endif
err = g->ops.mm.cache.l2_flush(g, false);
if (err != 0) {
nvgpu_err(g, "l2_flush failed");
@@ -554,10 +556,12 @@ int nvgpu_mm_setup_hw(struct gk20a *g)
g->ops.fb.set_mmu_page_size(g);
}
#ifdef CONFIG_NVGPU_COMPRESSION
if (g->ops.fb.set_use_full_comp_tag_line != NULL) {
mm->use_full_comp_tag_line =
g->ops.fb.set_use_full_comp_tag_line(g);
}
#endif
g->ops.fb.init_hw(g);

22
drivers/gpu/nvgpu/common/mm/vm.c
View File

@@ -45,14 +45,18 @@ struct nvgpu_ctag_buffer_info {
u32 pgsz_idx;
u32 flags;
#ifdef CONFIG_NVGPU_COMPRESSION
s16 compr_kind;
#endif
s16 incompr_kind;
u32 ctag_lines;
};
#ifdef CONFIG_NVGPU_COMPRESSION
static int nvgpu_vm_compute_compression(struct vm_gk20a *vm,
struct nvgpu_ctag_buffer_info *binfo);
#endif
static void nvgpu_vm_do_unmap(struct nvgpu_mapped_buf *mapped_buffer,
struct vm_gk20a_mapping_batch *batch);
@@ -1004,18 +1008,23 @@ int nvgpu_vm_map(struct vm_gk20a *vm,
binfo.flags = flags;
binfo.size = nvgpu_os_buf_get_size(os_buf);
binfo.incompr_kind = incompr_kind;
#ifdef CONFIG_NVGPU_COMPRESSION
if (vm->enable_ctag && compr_kind != NVGPU_KIND_INVALID) {
binfo.compr_kind = compr_kind;
} else {
binfo.compr_kind = NVGPU_KIND_INVALID;
}
binfo.incompr_kind = incompr_kind;
if (compr_kind != NVGPU_KIND_INVALID) {
map_key_kind = compr_kind;
} else {
map_key_kind = incompr_kind;
}
#else
map_key_kind = incompr_kind;
#endif
/*
* Check if this buffer is already mapped.
@@ -1081,6 +1090,7 @@ int nvgpu_vm_map(struct vm_gk20a *vm,
va_allocated = false;
}
#ifdef CONFIG_NVGPU_COMPRESSION
err = nvgpu_vm_compute_compression(vm, &binfo);
if (err != 0) {
nvgpu_err(g, "failure setting up compression");
@@ -1176,7 +1186,9 @@ int nvgpu_vm_map(struct vm_gk20a *vm,
nvgpu_assert((binfo.compr_kind >= 0) &&
(binfo.compr_kind <= (s16)U8_MAX));
pte_kind = (u8)binfo.compr_kind;
} else if (binfo.incompr_kind != NVGPU_KIND_INVALID) {
} else
#endif
if (binfo.incompr_kind != NVGPU_KIND_INVALID) {
/*
* Incompressible kind, ctag offset will not be programmed
*/
@@ -1193,9 +1205,11 @@ int nvgpu_vm_map(struct vm_gk20a *vm,
goto clean_up;
}
#ifdef CONFIG_NVGPU_COMPRESSION
if (clear_ctags) {
clear_ctags = gk20a_comptags_start_clear(os_buf);
}
#endif
map_addr = g->ops.mm.gmmu.map(vm,
map_addr,
@@ -1213,9 +1227,11 @@ int nvgpu_vm_map(struct vm_gk20a *vm,
batch,
aperture);
#ifdef CONFIG_NVGPU_COMPRESSION
if (clear_ctags) {
gk20a_comptags_finish_clear(os_buf, map_addr != 0U);
}
#endif
if (map_addr == 0ULL) {
err = -ENOMEM;
@@ -1405,6 +1421,7 @@ done:
return;
}
#ifdef CONFIG_NVGPU_COMPRESSION
static int nvgpu_vm_compute_compression(struct vm_gk20a *vm,
struct nvgpu_ctag_buffer_info *binfo)
{
@@ -1432,3 +1449,4 @@ static int nvgpu_vm_compute_compression(struct vm_gk20a *vm,
return 0;
}
#endif

3
drivers/gpu/nvgpu/common/vgpu/cbc/cbc_vgpu.h
View File

@@ -23,9 +23,12 @@
#ifndef NVGPU_CBC_VGPU_H
#define NVGPU_CBC_VGPU_H
#ifdef CONFIG_NVGPU_COMPRESSION
struct gk20a;
struct nvgpu_cbc;
int vgpu_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc);
#endif
#endif /* NVGPU_CBC_VGPU_H */

8
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -121,12 +121,14 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.en_illegal_compstat = NULL,
},
},
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc = {
.init = NULL,
.alloc_comptags = vgpu_cbc_alloc_comptags,
.ctrl = NULL,
.fix_config = NULL,
},
#endif
.ce = {
.isr_stall = NULL,
.isr_nonstall = NULL,
@@ -378,10 +380,12 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.init_hw = NULL,
.init_fs_state = NULL,
.set_mmu_page_size = NULL,
#ifdef CONFIG_NVGPU_COMPRESSION
.set_use_full_comp_tag_line = NULL,
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
#endif
.vpr_info_fetch = NULL,
.dump_vpr_info = NULL,
.dump_wpr_info = NULL,
@@ -589,7 +593,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.fb_flush = vgpu_mm_fb_flush,
.l2_invalidate = vgpu_mm_l2_invalidate,
.l2_flush = vgpu_mm_l2_flush,
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc_clean = NULL,
#endif
},
.gmmu = {
.map = vgpu_locked_gmmu_map,
@@ -775,7 +781,9 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
gops->ltc = vgpu_gp10b_ops.ltc;
#ifdef CONFIG_NVGPU_COMPRESSION
gops->cbc = vgpu_gp10b_ops.cbc;
#endif
gops->ce = vgpu_gp10b_ops.ce;
gops->gr = vgpu_gp10b_ops.gr;
gops->gpu_class = vgpu_gp10b_ops.gpu_class;

8
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -149,11 +149,13 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.en_illegal_compstat = NULL,
},
},
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc = {
.init = NULL,
.ctrl = NULL,
.alloc_comptags = vgpu_cbc_alloc_comptags,
},
#endif
.ce = {
.isr_stall = NULL,
.isr_nonstall = NULL,
@@ -444,10 +446,12 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.init_hw = NULL,
.init_fs_state = NULL,
.set_mmu_page_size = NULL,
#ifdef CONFIG_NVGPU_COMPRESSION
.set_use_full_comp_tag_line = NULL,
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
#endif
.vpr_info_fetch = NULL,
.dump_vpr_info = NULL,
.dump_wpr_info = NULL,
@@ -685,7 +689,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.fb_flush = vgpu_mm_fb_flush,
.l2_invalidate = vgpu_mm_l2_invalidate,
.l2_flush = vgpu_mm_l2_flush,
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc_clean = NULL,
#endif
},
.gmmu = {
.map = vgpu_locked_gmmu_map,
@@ -870,7 +876,9 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
gops->ltc = vgpu_gv11b_ops.ltc;
#ifdef CONFIG_NVGPU_COMPRESSION
gops->cbc = vgpu_gv11b_ops.cbc;
#endif
gops->ce = vgpu_gv11b_ops.ce;
gops->gr = vgpu_gv11b_ops.gr;
gops->gpu_class = vgpu_gv11b_ops.gpu_class;

2
drivers/gpu/nvgpu/common/vgpu/init/init_vgpu.c
View File

@@ -195,11 +195,13 @@ int vgpu_finalize_poweron_common(struct gk20a *g)
return err;
}
#ifdef CONFIG_NVGPU_COMPRESSION
err = nvgpu_cbc_init_support(g);
if (err != 0) {
nvgpu_err(g, "failed to init cbc");
return err;
}
#endif
g->ops.chip_init_gpu_characteristics(g);

2
drivers/gpu/nvgpu/common/vgpu/vgpu.c
View File

@@ -448,11 +448,13 @@ int vgpu_finalize_poweron_common(struct gk20a *g)
return err;
}
#ifdef CONFIG_NVGPU_COMPRESSION
err = nvgpu_cbc_init_support(g);
if (err != 0) {
nvgpu_err(g, "failed to init cbc");
return err;
}
#endif
g->ops.chip_init_gpu_characteristics(g);

3
drivers/gpu/nvgpu/hal/cbc/cbc_gm20b.h
View File

@@ -25,6 +25,8 @@
#ifndef NVGPU_CBC_GM20B
#define NVGPU_CBC_GM20B
#ifdef CONFIG_NVGPU_COMPRESSION
#include <nvgpu/types.h>
struct gk20a;
@@ -43,3 +45,4 @@ int gm20b_cbc_alloc_virtc(struct gk20a *g,
size_t compbit_backing_size);
#endif
#endif

4
drivers/gpu/nvgpu/hal/cbc/cbc_gp10b.h
View File

@@ -22,6 +22,9 @@
#ifndef CBC_GP10B_H
#define CBC_GP10B_H
#ifdef CONFIG_NVGPU_COMPRESSION
struct gk20a;
struct nvgpu_cbc;
@@ -31,3 +34,4 @@ int gp10b_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc);
int gp10b_cbc_ctrl(struct gk20a *g, enum nvgpu_cbc_op op, u32 min, u32 max);
#endif
#endif

4
drivers/gpu/nvgpu/hal/cbc/cbc_gv11b.h
View File

@@ -22,9 +22,13 @@
#ifndef CBC_GV11B_H
#define CBC_GV11B_H
#ifdef CONFIG_NVGPU_COMPRESSION
struct gk20a;
struct nvgpu_cbc;
void gv11b_cbc_init(struct gk20a *g, struct nvgpu_cbc *cbc);
#endif
#endif

3
drivers/gpu/nvgpu/hal/cbc/cbc_tu104.h
View File

@@ -23,6 +23,8 @@
#ifndef CBC_TU104_H
#define CBC_TU104_H
#ifdef CONFIG_NVGPU_COMPRESSION
#include <nvgpu/types.h>
enum nvgpu_cbc_op;
@@ -36,3 +38,4 @@ int tu104_cbc_ctrl(struct gk20a *g, enum nvgpu_cbc_op op,
void tu104_cbc_init(struct gk20a *g, struct nvgpu_cbc *cbc);
#endif
#endif

23
drivers/gpu/nvgpu/hal/fb/fb_gm20b.c
View File

@@ -176,16 +176,6 @@ void gm20b_fb_set_mmu_page_size(struct gk20a *g)
gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
}
bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g)
{
/* set large page size in fb */
u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r());
fb_mmu_ctrl |= fb_mmu_ctrl_use_full_comp_tag_line_true_f();
gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
return true;
}
u32 gm20b_fb_mmu_ctrl(struct gk20a *g)
{
return gk20a_readl(g, fb_mmu_ctrl_r());
@@ -206,6 +196,18 @@ u32 gm20b_fb_mmu_debug_rd(struct gk20a *g)
return gk20a_readl(g, fb_mmu_debug_rd_r());
}
#ifdef CONFIG_NVGPU_COMPRESSION
bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g)
{
/* set large page size in fb */
u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r());
fb_mmu_ctrl |= fb_mmu_ctrl_use_full_comp_tag_line_true_f();
gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
return true;
}
u64 gm20b_fb_compression_page_size(struct gk20a *g)
{
return SZ_128K;
@@ -220,6 +222,7 @@ u64 gm20b_fb_compression_align_mask(struct gk20a *g)
{
return SZ_64K - 1UL;
}
#endif
void gm20b_fb_dump_vpr_info(struct gk20a *g)
{

4
drivers/gpu/nvgpu/hal/fb/fb_gm20b.h
View File

@@ -34,14 +34,16 @@ void gm20b_fb_init_hw(struct gk20a *g);
int gm20b_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
void fb_gm20b_init_fs_state(struct gk20a *g);
void gm20b_fb_set_mmu_page_size(struct gk20a *g);
bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g);
u32 gm20b_fb_mmu_ctrl(struct gk20a *g);
u32 gm20b_fb_mmu_debug_ctrl(struct gk20a *g);
u32 gm20b_fb_mmu_debug_wr(struct gk20a *g);
u32 gm20b_fb_mmu_debug_rd(struct gk20a *g);
#ifdef CONFIG_NVGPU_COMPRESSION
bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g);
u64 gm20b_fb_compression_page_size(struct gk20a *g);
unsigned int gm20b_fb_compressible_page_size(struct gk20a *g);
u64 gm20b_fb_compression_align_mask(struct gk20a *g);
#endif
void gm20b_fb_dump_vpr_info(struct gk20a *g);
void gm20b_fb_dump_wpr_info(struct gk20a *g);
void gm20b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size);

2
drivers/gpu/nvgpu/hal/fb/fb_gp10b.c
View File

@@ -27,6 +27,7 @@
#include "fb_gp10b.h"
#ifdef CONFIG_NVGPU_COMPRESSION
u64 gp10b_fb_compression_page_size(struct gk20a *g)
{
return SZ_64K;
@@ -36,3 +37,4 @@ unsigned int gp10b_fb_compressible_page_size(struct gk20a *g)
{
return (unsigned int)SZ_4K;
}
#endif

2
drivers/gpu/nvgpu/hal/fb/fb_gp10b.h
View File

@@ -26,7 +26,9 @@
#define NVGPU_FB_GP10B_H
struct gk20a;
#ifdef CONFIG_NVGPU_COMPRESSION
u64 gp10b_fb_compression_page_size(struct gk20a *g);
unsigned int gp10b_fb_compressible_page_size(struct gk20a *g);
#endif
#endif /* NVGPU_FB_GP10B_H */

2
drivers/gpu/nvgpu/hal/fb/fb_gv11b.c
View File

@@ -117,6 +117,7 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
}
}
#ifdef CONFIG_NVGPU_COMPRESSION
void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
{
u32 compbit_base_post_divide;
@@ -167,3 +168,4 @@ void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
cbc->compbit_store.base_hw = compbit_base_post_divide;
}
#endif

7
drivers/gpu/nvgpu/hal/fb/fb_gv11b.h
View File

@@ -26,11 +26,14 @@
#define NVGPU_FB_GV11B_H
struct gk20a;
struct nvgpu_cbc;
void gv11b_fb_init_hw(struct gk20a *g);
void gv11b_fb_init_fs_state(struct gk20a *g);
void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc);
void gv11b_fb_reset(struct gk20a *g);
#ifdef CONFIG_NVGPU_COMPRESSION
struct nvgpu_cbc;
void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc);
#endif
#endif /* NVGPU_FB_GV11B_H */

2
drivers/gpu/nvgpu/hal/fb/fb_tu104.c
View File

@@ -101,6 +101,7 @@ int fb_tu104_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
return err;
}
#ifdef CONFIG_NVGPU_COMPRESSION
void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
{
u64 base_divisor;
@@ -147,6 +148,7 @@ void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
cbc->compbit_store.base_hw = compbit_store_base;
}
#endif
static int tu104_fb_wait_mmu_bind(struct gk20a *g)
{

4
drivers/gpu/nvgpu/hal/fb/fb_tu104.h
View File

@@ -27,10 +27,12 @@
struct gk20a;
struct nvgpu_mem;
struct nvgpu_cbc;
int fb_tu104_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
#ifdef CONFIG_NVGPU_COMPRESSION
struct nvgpu_cbc;
void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc);
#endif
int tu104_fb_apply_pdb_cache_war(struct gk20a *g);
size_t tu104_fb_get_vidmem_size(struct gk20a *g);
int tu104_fb_enable_nvlink(struct gk20a *g);

12
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -139,12 +139,14 @@ static const struct gpu_ops gm20b_ops = {
.en_illegal_compstat = NULL,
},
},
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc = {
.init = gm20b_cbc_init,
.ctrl = gm20b_cbc_ctrl,
.alloc_comptags = gm20b_cbc_alloc_comptags,
.fix_config = gm20b_cbc_fix_config,
},
#endif
.ce = {
.isr_stall = gk20a_ce2_stall_isr,
.isr_nonstall = gk20a_ce2_nonstall_isr,
@@ -518,15 +520,17 @@ static const struct gpu_ops gm20b_ops = {
.init_hw = gm20b_fb_init_hw,
.init_fs_state = fb_gm20b_init_fs_state,
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
#ifdef CONFIG_NVGPU_COMPRESSION
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.compression_page_size = gm20b_fb_compression_page_size,
.compressible_page_size = gm20b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
#endif
.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
.dump_vpr_info = gm20b_fb_dump_vpr_info,
.dump_wpr_info = gm20b_fb_dump_wpr_info,
@@ -779,7 +783,9 @@ static const struct gpu_ops gm20b_ops = {
.fb_flush = gk20a_mm_fb_flush,
.l2_invalidate = gk20a_mm_l2_invalidate,
.l2_flush = gk20a_mm_l2_flush,
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc_clean = gk20a_mm_cbc_clean,
#endif
},
.gmmu = {
.get_mmu_levels = gk20a_mm_get_mmu_levels,
@@ -1015,7 +1021,9 @@ int gm20b_init_hal(struct gk20a *g)
struct gpu_ops *gops = &g->ops;
gops->ltc = gm20b_ops.ltc;
#ifdef CONFIG_NVGPU_COMPRESSION
gops->cbc = gm20b_ops.cbc;
#endif
gops->ce = gm20b_ops.ce;
gops->gr = gm20b_ops.gr;
gops->gpu_class = gm20b_ops.gpu_class;

12
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -168,12 +168,14 @@ static const struct gpu_ops gp10b_ops = {
.en_illegal_compstat = NULL,
},
},
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc = {
.init = gm20b_cbc_init,
.alloc_comptags = gp10b_cbc_alloc_comptags,
.ctrl = gp10b_cbc_ctrl,
.fix_config = gm20b_cbc_fix_config,
},
#endif
.ce = {
.isr_stall = gp10b_ce_stall_isr,
.isr_nonstall = gp10b_ce_nonstall_isr,
@@ -585,15 +587,17 @@ static const struct gpu_ops gp10b_ops = {
.init_hw = gm20b_fb_init_hw,
.init_fs_state = fb_gm20b_init_fs_state,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
#ifdef CONFIG_NVGPU_COMPRESSION
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
#endif
.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
.dump_vpr_info = gm20b_fb_dump_vpr_info,
.dump_wpr_info = gm20b_fb_dump_wpr_info,
@@ -865,7 +869,9 @@ static const struct gpu_ops gp10b_ops = {
.fb_flush = gk20a_mm_fb_flush,
.l2_invalidate = gk20a_mm_l2_invalidate,
.l2_flush = gk20a_mm_l2_flush,
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc_clean = gk20a_mm_cbc_clean,
#endif
},
.gmmu = {
.get_mmu_levels = gp10b_mm_get_mmu_levels,
@@ -1106,7 +1112,9 @@ int gp10b_init_hal(struct gk20a *g)
struct gpu_ops *gops = &g->ops;
gops->ltc = gp10b_ops.ltc;
#ifdef CONFIG_NVGPU_COMPRESSION
gops->cbc = gp10b_ops.cbc;
#endif
gops->ce = gp10b_ops.ce;
gops->gr = gp10b_ops.gr;
gops->gpu_class = gp10b_ops.gpu_class;

14
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -207,11 +207,13 @@ static const struct gpu_ops gv11b_ops = {
gv11b_ltc_intr_en_illegal_compstat,
}
},
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc = {
.init = gv11b_cbc_init,
.alloc_comptags = gp10b_cbc_alloc_comptags,
.ctrl = gp10b_cbc_ctrl,
},
#endif
.ce = {
.isr_stall = gv11b_ce_stall_isr,
.isr_nonstall = gp10b_ce_nonstall_isr,
@@ -690,17 +692,19 @@ static const struct gpu_ops gv11b_ops = {
gv11b_fb_intr_get_hubmmu_err_desc,
.init_hw = gv11b_fb_init_hw,
.init_fs_state = gv11b_fb_init_fs_state,
.cbc_configure = gv11b_fb_cbc_configure,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc_configure = gv11b_fb_cbc_configure,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
#endif
.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
.dump_vpr_info = gm20b_fb_dump_vpr_info,
.dump_wpr_info = gm20b_fb_dump_wpr_info,
@@ -1017,7 +1021,9 @@ static const struct gpu_ops gv11b_ops = {
.fb_flush = gk20a_mm_fb_flush,
.l2_invalidate = gk20a_mm_l2_invalidate,
.l2_flush = gv11b_mm_l2_flush,
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc_clean = gk20a_mm_cbc_clean,
#endif
},
.gmmu = {
.get_mmu_levels = gp10b_mm_get_mmu_levels,
@@ -1279,7 +1285,9 @@ int gv11b_init_hal(struct gk20a *g)
struct gpu_ops *gops = &g->ops;
gops->ltc = gv11b_ops.ltc;
#ifdef CONFIG_NVGPU_COMPRESSION
gops->cbc = gv11b_ops.cbc;
#endif
gops->ce = gv11b_ops.ce;
gops->gr = gv11b_ops.gr;
gops->gpu_class = gv11b_ops.gpu_class;

16
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -249,6 +249,7 @@ static const struct gpu_ops tu104_ops = {
gv11b_ltc_intr_en_illegal_compstat,
}
},
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc = {
.init = tu104_cbc_init,
.get_base_divisor = tu104_cbc_get_base_divisor,
@@ -256,6 +257,7 @@ static const struct gpu_ops tu104_ops = {
.ctrl = tu104_cbc_ctrl,
.fix_config = NULL,
},
#endif
.ce = {
.isr_stall = gv11b_ce_stall_isr,
.isr_nonstall = NULL,
@@ -726,17 +728,19 @@ static const struct gpu_ops tu104_ops = {
.fb = {
.init_hw = gv11b_fb_init_hw,
.init_fs_state = gp106_fb_init_fs_state,
.cbc_configure = tu104_fb_cbc_configure,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc_configure = tu104_fb_cbc_configure,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
#endif
.vpr_info_fetch = NULL,
.dump_vpr_info = NULL,
.dump_wpr_info = gm20b_fb_dump_wpr_info,
@@ -1059,7 +1063,9 @@ static const struct gpu_ops tu104_ops = {
.fb_flush = gk20a_mm_fb_flush,
.l2_invalidate = gk20a_mm_l2_invalidate,
.l2_flush = gv11b_mm_l2_flush,
#ifdef CONFIG_NVGPU_COMPRESSION
.cbc_clean = gk20a_mm_cbc_clean,
#endif
},
.gmmu = {
.get_mmu_levels = gp10b_mm_get_mmu_levels,
@@ -1412,7 +1418,9 @@ int tu104_init_hal(struct gk20a *g)
gops->bios = tu104_ops.bios;
gops->ltc = tu104_ops.ltc;
#ifdef CONFIG_NVGPU_COMPRESSION
gops->cbc = tu104_ops.cbc;
#endif
gops->ce = tu104_ops.ce;
gops->gr = tu104_ops.gr;
gops->gpu_class = tu104_ops.gpu_class;
@@ -1514,9 +1522,11 @@ int tu104_init_hal(struct gk20a *g)
/* dGpu VDK support */
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)){
/* Disable compression */
#ifdef CONFIG_NVGPU_COMPRESSION
gops->cbc.init = NULL;
gops->cbc.ctrl = NULL;
gops->cbc.alloc_comptags = NULL;
#endif
gops->gr.falcon.load_ctxsw_ucode =
nvgpu_gr_falcon_load_ctxsw_ucode;

1
drivers/gpu/nvgpu/hal/ltc/ltc_tu104.c
View File

@@ -22,7 +22,6 @@
#include <nvgpu/types.h>
#include <nvgpu/ltc.h>
#include <nvgpu/comptags.h>
#include <nvgpu/io.h>
#include <nvgpu/timers.h>
#include <nvgpu/gk20a.h>

2
drivers/gpu/nvgpu/hal/mm/cache/flush_gk20a.c vendored
View File

@@ -215,6 +215,7 @@ hw_was_off:
return err;
}
#ifdef CONFIG_NVGPU_COMPRESSION
void gk20a_mm_cbc_clean(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
@@ -262,3 +263,4 @@ void gk20a_mm_cbc_clean(struct gk20a *g)
hw_was_off:
gk20a_idle_nosuspend(g);
}
#endif

2
drivers/gpu/nvgpu/hal/mm/cache/flush_gk20a.h vendored
View File

@@ -29,7 +29,9 @@ struct gk20a;
int gk20a_mm_fb_flush(struct gk20a *g);
int gk20a_mm_l2_flush(struct gk20a *g, bool invalidate);
#ifdef CONFIG_NVGPU_COMPRESSION
void gk20a_mm_cbc_clean(struct gk20a *g);
#endif
void gk20a_mm_l2_invalidate(struct gk20a *g);
#endif

40
drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c
View File

@@ -112,7 +112,6 @@ static void update_pte(struct vm_gk20a *vm,
struct nvgpu_gmmu_attrs *attrs)
{
struct gk20a *g = gk20a_from_vm(vm);
u32 page_size = vm->gmmu_page_sizes[attrs->pgsz];
u32 pte_valid = attrs->valid ?
gmmu_pte_valid_true_f() :
gmmu_pte_valid_false_f();
@@ -120,14 +119,19 @@ static void update_pte(struct vm_gk20a *vm,
u32 addr = attrs->aperture == APERTURE_SYSMEM ?
gmmu_pte_address_sys_f(phys_shifted) :
gmmu_pte_address_vid_f(phys_shifted);
#ifdef CONFIG_NVGPU_COMPRESSION
u32 page_size = vm->gmmu_page_sizes[attrs->pgsz];
u32 ctag_shift = 0;
u64 compression_page_size = g->ops.fb.compression_page_size(g);
u64 compression_page_size;
if (compression_page_size == 0U) {
compression_page_size = g->ops.fb.compression_page_size(g);
if (compression_page_size == 0ULL) {
nvgpu_err(g, "compression_page_size is 0");
} else {
ctag_shift = (u32)ilog2(compression_page_size);
}
#endif
pte_w[0] = pte_valid | addr;
@@ -139,9 +143,11 @@ static void update_pte(struct vm_gk20a *vm,
gmmu_pte_aperture_sys_mem_ncoh_f(),
gmmu_pte_aperture_sys_mem_coh_f(),
gmmu_pte_aperture_video_memory_f()) |
gmmu_pte_kind_f(attrs->kind_v) |
gmmu_pte_comptagline_f((U32(attrs->ctag) >> U32(ctag_shift)));
gmmu_pte_kind_f(attrs->kind_v);
#ifdef CONFIG_NVGPU_COMPRESSION
pte_w[1] |=
gmmu_pte_comptagline_f((U32(attrs->ctag) >> U32(ctag_shift)));
if ((attrs->ctag != 0ULL) &&
vm->mm->use_full_comp_tag_line &&
((phys_addr & 0x10000ULL) != 0ULL)) {
@@ -149,6 +155,11 @@ static void update_pte(struct vm_gk20a *vm,
BIT32(gmmu_pte_comptagline_s() - 1U));
}
if (attrs->ctag != 0ULL) {
attrs->ctag += page_size;
}
#endif
if (attrs->rw_flag == gk20a_mem_flag_read_only) {
pte_w[0] |= gmmu_pte_read_only_true_f();
pte_w[1] |= gmmu_pte_write_disable_true_f();
@@ -161,10 +172,6 @@ static void update_pte(struct vm_gk20a *vm,
if (!attrs->cacheable) {
pte_w[1] |= gmmu_pte_vol_true_f();
}
if (attrs->ctag != 0ULL) {
attrs->ctag += page_size;
}
}
static void update_gmmu_pte_locked(struct vm_gk20a *vm,
@@ -179,14 +186,19 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
u32 page_size = vm->gmmu_page_sizes[attrs->pgsz];
u32 pd_offset = nvgpu_pd_offset_from_index(l, pd_idx);
u32 pte_w[2] = {0, 0};
u32 ctag_shift = 0;
u64 compression_page_size = g->ops.fb.compression_page_size(g);
if (compression_page_size == 0U) {
#ifdef CONFIG_NVGPU_COMPRESSION
u64 compression_page_size;
u32 ctag_shift = 0;
compression_page_size = g->ops.fb.compression_page_size(g);
if (compression_page_size == 0ULL) {
nvgpu_err(g, "compression_page_size is 0");
} else {
ctag_shift = (u32)ilog2(compression_page_size);
}
#endif
if (phys_addr != 0ULL) {
update_pte(vm, pte_w, phys_addr, attrs);
@@ -200,7 +212,9 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
"PTE: i=%-4u size=%-2u offs=%-4u | "
"GPU %#-12llx phys %#-12llx "
"pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c "
#ifdef CONFIG_NVGPU_COMPRESSION
"ctag=0x%08x "
#endif
"[0x%08x, 0x%08x]",
pd_idx, l->entry_size, pd_offset,
virt_addr, phys_addr,
@@ -212,7 +226,9 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
attrs->sparse ? 'S' : '-',
attrs->priv ? 'P' : '-',
attrs->valid ? 'V' : '-',
#ifdef CONFIG_NVGPU_COMPRESSION
U32(attrs->ctag) >> U32(ctag_shift),
#endif
pte_w[1], pte_w[0]);
nvgpu_pd_write(g, pd, (size_t)pd_offset + (size_t)0, pte_w[0]);

22
drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gp10b.c
View File

@@ -174,8 +174,10 @@ static void update_pte(struct vm_gk20a *vm,
struct nvgpu_gmmu_attrs *attrs)
{
struct gk20a *g = gk20a_from_vm(vm);
#ifdef CONFIG_NVGPU_COMPRESSION
u64 ctag_granularity = g->ops.fb.compression_page_size(g);
u32 page_size = vm->gmmu_page_sizes[attrs->pgsz];
#endif
u32 pte_valid = attrs->valid ?
gmmu_new_pte_valid_true_f() :
gmmu_new_pte_valid_false_f();
@@ -200,10 +202,17 @@ static void update_pte(struct vm_gk20a *vm,
tmp_addr = phys_addr >> (24U + gmmu_new_pte_address_shift_v());
nvgpu_assert(u64_hi32(tmp_addr) == 0U);
pte_w[1] = (u32)tmp_addr |
gmmu_new_pte_kind_f(attrs->kind_v) |
gmmu_new_pte_comptagline_f((u32)(attrs->ctag /
gmmu_new_pte_kind_f(attrs->kind_v);
#ifdef CONFIG_NVGPU_COMPRESSION
pte_w[1] |= gmmu_new_pte_comptagline_f((u32)(attrs->ctag /
ctag_granularity));
if (attrs->ctag != 0ULL) {
attrs->ctag += page_size;
}
#endif
if (attrs->rw_flag == gk20a_mem_flag_read_only) {
pte_w[0] |= gmmu_new_pte_read_only_true_f();
}
@@ -215,11 +224,6 @@ static void update_pte(struct vm_gk20a *vm,
pte_w[0] |= gmmu_new_pte_vol_true_f();
}
}
if (attrs->ctag != 0ULL) {
attrs->ctag += page_size;
}
}
static void update_pte_sparse(u32 *pte_w)
@@ -254,7 +258,9 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
"PTE: i=%-4u size=%-2u | "
"GPU %#-12llx phys %#-12llx "
"pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c%c "
#ifdef CONFIG_NVGPU_COMPRESSION
"ctag=0x%08llx "
#endif
"[0x%08x, 0x%08x]",
vm->name,
pd_idx, l->entry_size,
@@ -268,7 +274,9 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
attrs->priv ? 'P' : '-',
attrs->valid ? 'V' : '-',
attrs->platform_atomic ? 'A' : '-',
#ifdef CONFIG_NVGPU_COMPRESSION
attrs->ctag / g->ops.fb.compression_page_size(g),
#endif
pte_w[1], pte_w[0]);
nvgpu_pd_write(g, pd, (size_t)pd_offset + (size_t)0, pte_w[0]);

4
drivers/gpu/nvgpu/include/nvgpu/cbc.h
View File

@@ -23,6 +23,8 @@
#ifndef NVGPU_CBC_H
#define NVGPU_CBC_H
#ifdef CONFIG_NVGPU_COMPRESSION
#include <nvgpu/types.h>
#include <nvgpu/comptags.h>
#include <nvgpu/nvgpu_mem.h>
@@ -58,5 +60,5 @@ int nvgpu_cbc_init_support(struct gk20a *g);
void nvgpu_cbc_remove_support(struct gk20a *g);
int nvgpu_cbc_alloc(struct gk20a *g, size_t compbit_backing_size,
bool vidmem_alloc);
#endif
#endif /* NVGPU_CBC_H */

4
drivers/gpu/nvgpu/include/nvgpu/comptags.h
View File

@@ -23,6 +23,8 @@
#ifndef NVGPU_COMPTAGS_H
#define NVGPU_COMPTAGS_H
#ifdef CONFIG_NVGPU_COMPRESSION
#include <nvgpu/lock.h>
#include <nvgpu/types.h>
@@ -99,5 +101,5 @@ void gk20a_get_comptags(struct nvgpu_os_buffer *buf,
bool gk20a_comptags_start_clear(struct nvgpu_os_buffer *buf);
void gk20a_comptags_finish_clear(struct nvgpu_os_buffer *buf,
bool clear_successful);
#endif
#endif /* NVGPU_COMPTAGS_H */

12
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -76,7 +76,6 @@ struct nvgpu_engine_status_info;
struct nvgpu_pbdma_status_info;
struct nvgpu_gr_config;
struct nvgpu_fecs_method_op;
struct nvgpu_cbc;
struct nvgpu_mem;
struct gk20a_cs_snapshot_client;
struct dbg_session_gk20a;
@@ -247,6 +246,7 @@ struct gpu_ops {
bool enable);
} intr;
} ltc;
#ifdef CONFIG_NVGPU_COMPRESSION
struct {
void (*init)(struct gk20a *g, struct nvgpu_cbc *cbc);
u64 (*get_base_divisor)(struct gk20a *g);
@@ -256,6 +256,7 @@ struct gpu_ops {
u32 min, u32 max);
u32 (*fix_config)(struct gk20a *g, int base);
} cbc;
#endif
struct {
void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base);
u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base);
@@ -880,17 +881,19 @@ struct gpu_ops {
struct nvgpu_hw_err_inject_info_desc * (*get_hubmmu_err_desc)
(struct gk20a *g);
void (*init_hw)(struct gk20a *g);
void (*cbc_configure)(struct gk20a *g, struct nvgpu_cbc *cbc);
void (*init_fs_state)(struct gk20a *g);
void (*init_uncompressed_kind_map)(struct gk20a *g);
void (*init_kind_attr)(struct gk20a *g);
void (*set_mmu_page_size)(struct gk20a *g);
bool (*set_use_full_comp_tag_line)(struct gk20a *g);
u32 (*mmu_ctrl)(struct gk20a *g);
u32 (*mmu_debug_ctrl)(struct gk20a *g);
u32 (*mmu_debug_wr)(struct gk20a *g);
u32 (*mmu_debug_rd)(struct gk20a *g);
#ifdef CONFIG_NVGPU_COMPRESSION
void (*cbc_configure)(struct gk20a *g, struct nvgpu_cbc *cbc);
bool (*set_use_full_comp_tag_line)(struct gk20a *g);
/*
* Compression tag line coverage. When mapping a compressible
* buffer, ctagline is increased when the virtual address
@@ -908,6 +911,7 @@ struct gpu_ops {
* address bits that must match.
*/
u64 (*compression_align_mask)(struct gk20a *g);
#endif
void (*dump_vpr_info)(struct gk20a *g);
void (*dump_wpr_info)(struct gk20a *g);
@@ -1283,7 +1287,9 @@ struct gpu_ops {
int (*fb_flush)(struct gk20a *g);
void (*l2_invalidate)(struct gk20a *g);
int (*l2_flush)(struct gk20a *g, bool invalidate);
#ifdef CONFIG_NVGPU_COMPRESSION
void (*cbc_clean)(struct gk20a *g);
#endif
} cache;
struct {
const struct gk20a_mmu_level *

2
drivers/gpu/nvgpu/include/nvgpu/gmmu.h
View File

@@ -78,7 +78,9 @@ enum gk20a_mem_rw_flag {
struct nvgpu_gmmu_attrs {
u32 pgsz;
u32 kind_v;
#ifdef CONFIG_NVGPU_COMPRESSION
u64 ctag;
#endif
bool cacheable;
enum gk20a_mem_rw_flag rw_flag;
bool sparse;

2
userspace/units/mm/gmmu/page_table/page_table.c
View File

@@ -306,7 +306,9 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
g->ops.mm.is_bar1_supported = gv11b_mm_is_bar1_supported;
g->ops.mm.cache.l2_flush = gv11b_mm_l2_flush;
g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush;
#ifdef CONFIG_NVGPU_COMPRESSION
g->ops.fb.compression_page_size = gp10b_fb_compression_page_size;
#endif
g->ops.fb.tlb_invalidate = gm20b_fb_tlb_invalidate;
g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;

2
userspace/units/mm/page_table_faults/page_table_faults.c
View File

@@ -126,7 +126,9 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
g->ops.mm.gmmu.map = nvgpu_gmmu_map_locked;
g->ops.mm.gmmu.unmap = nvgpu_gmmu_unmap_locked;
g->ops.mm.gmmu.gpu_phys_addr = gv11b_gpu_phys_addr;
#ifdef CONFIG_NVGPU_COMPRESSION
g->ops.fb.compression_page_size = gp10b_fb_compression_page_size;
#endif
g->ops.fb.tlb_invalidate = gm20b_fb_tlb_invalidate;
g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;

13
userspace/units/mm/vm/vm.c
View File

@@ -133,7 +133,9 @@ static int init_test_env(struct unit_module *m, struct gk20a *g)
nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, true);
#ifdef CONFIG_NVGPU_COMPRESSION
g->ops.fb.compression_page_size = gp10b_fb_compression_page_size;
#endif
g->ops.fb.tlb_invalidate = gm20b_fb_tlb_invalidate;
g->ops.mm.gmmu.get_default_big_page_size =
@@ -148,6 +150,8 @@ static int init_test_env(struct unit_module *m, struct gk20a *g)
return UNIT_SUCCESS;
}
#define NV_KIND_INVALID -1
/*
* Try mapping a buffer into the GPU virtual address space:
* - Allocate a new CPU buffer
@@ -175,6 +179,7 @@ static int map_buffer(struct unit_module *m,
struct nvgpu_mem mem = {0};
struct nvgpu_sgt *sgt = NULL;
bool fixed_gpu_va = (gpu_va != 0);
s16 compr_kind;
u32 pte[2];
if (vm == NULL) {
@@ -229,6 +234,12 @@ static int map_buffer(struct unit_module *m,
}
}
#ifdef CONFIG_NVGPU_COMPRESSION
compr_kind = 0;
#else
compr_kind = NV_KIND_INVALID;
#endif
ret = nvgpu_vm_map(vm,
&os_buf,
sgt,
@@ -237,7 +248,7 @@ static int map_buffer(struct unit_module *m,
0,
gk20a_mem_flag_none,
NVGPU_VM_MAP_CACHEABLE,
0,
compr_kind,
0,
batch,
APERTURE_SYSMEM,