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gpu: nvgpu: Cleanup for gr_gk20a header

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Removed unused struct from gr_gk20a.h
Change static allocation for struct gr_gk20a to dynamic type.
Change all the files that being affected by that change.

Call gr allocation from corresponding init_support functions, which
are part of the probe functions.
nvgpu_pci_init_support in pci.c
vgpu_init_support in vgpu_linux.c
gk20a_init_support in module.c

Call gr free before the gk20a free call in nvgpu_free_gk20a.

Rename struct gr_gk20a to struct nvgpu_gr

JIRA NVGPU-3132

Change-Id: Ief5e664521f141c7378c4044ed0df5f03ba06fca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095798
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-04-11 17:50:56 -07:00
committed by mobile promotions
parent 37253f8ccb
commit 556e139077
52 changed files with 406 additions and 353 deletions
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8
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
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@@ -266,7 +266,7 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
struct nvgpu_dbg_gpu_read_single_sm_error_state_args *args)
{
struct gk20a *g = dbg_s->g;
struct gr_gk20a *gr = &g->gr;
struct nvgpu_gr *gr = g->gr;
struct nvgpu_tsg_sm_error_state *sm_error_state;
struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record;
struct channel_gk20a *ch;
@@ -1101,7 +1101,7 @@ static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm(
nvgpu_mutex_acquire(&g->dbg_sessions_lock);
/* Suspend GPU context switching */
err = g->ops.gr.falcon.disable_ctxsw(g, g->gr.falcon);
err = g->ops.gr.falcon.disable_ctxsw(g, g->gr->falcon);
if (err) {
nvgpu_err(g, "unable to stop gr ctxsw");
/* this should probably be ctx-fatal... */
@@ -1119,7 +1119,7 @@ static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm(
break;
}
err = g->ops.gr.falcon.enable_ctxsw(g, g->gr.falcon);
err = g->ops.gr.falcon.enable_ctxsw(g, g->gr->falcon);
if (err)
nvgpu_err(g, "unable to restart ctxsw!");
@@ -1451,7 +1451,7 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state(
struct nvgpu_dbg_gpu_clear_single_sm_error_state_args *args)
{
struct gk20a *g = dbg_s->g;
struct gr_gk20a *gr = &g->gr;
struct nvgpu_gr *gr = g->gr;
u32 sm_id;
struct channel_gk20a *ch;
int err = 0;