diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 542ed1ffb..7993e0718 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1069,6 +1069,31 @@ static void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data)
 	gk20a_dbg_fn("done");
 }
 
+static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data)
+{
+	u32 val;
+	bool flag;
+
+	gk20a_dbg_fn("");
+
+	val = gk20a_readl(g, gr_gpcs_tpcs_tex_in_dbg_r());
+	flag = (data & NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE) ? 1 : 0;
+	val = set_field(val, gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(),
+			gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(flag));
+	gk20a_writel(g, gr_gpcs_tpcs_tex_in_dbg_r(), val);
+
+	val = gk20a_readl(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r());
+	flag = (data &
+		NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD) ? 1 : 0;
+	val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(),
+			gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(flag));
+	flag = (data &
+		NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST) ? 1 : 0;
+	val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(),
+			gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(flag));
+	gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val);
+}
+
 
 static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data)
 {
@@ -1120,6 +1145,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
 		case NVC097_SET_COALESCE_BUFFER_SIZE:
 			gr_gv11b_set_coalesce_buffer_size(g, data);
 			break;
+		case NVC397_SET_TEX_IN_DBG:
+			gr_gv11b_set_tex_in_dbg(g, data);
+			break;
 		default:
 			goto fail;
 		}
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 9283a5972..ff5782d95 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -39,6 +39,11 @@ enum {
 #define NVC397_SET_CIRCULAR_BUFFER_SIZE 	0x1280
 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 	0x02dc
 #define NVC397_SET_GO_IDLE_TIMEOUT 		0x022c
+#define NVC397_SET_TEX_IN_DBG			0x10bc
+
+#define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE		0x1
+#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD	0x2
+#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST	0x4
 
 #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 29a8b33c3..75a64be5e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -3830,6 +3830,38 @@ static inline u32 gr_zcull_subregion_qty_v(void)
 {
 	return 0x00000010;
 }
+static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void)
+{
+	return 0x00419a00;
+}
+static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v)
+{
+	return (v & 0x1) << 19;
+}
+static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void)
+{
+	return 0x1 << 19;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void)
+{
+	return 0x00419bf0;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void)
+{
+	return 0x1 << 5;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v)
+{
+	return (v & 0x1) << 10;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
+{
+	return 0x1 << 10;
+}
 static inline u32 gr_fe_pwr_mode_r(void)
 {
 	return 0x00404170;