From 55f472a0b7be1a64a7f76faf7285a03e9c798ae7 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 21 Oct 2020 10:54:17 +0530 Subject: [PATCH] gpu: nvgpu: Use logical GPC id mask Replaced logical GPC id mask instead of physical GPC id mask for GPCCS falcon index mask programming required for multi-GR boot. JIRA NVGPU-5650 Change-Id: I0fad31ea962d2f0bd069aa20deeea16ea29c307a Signed-off-by: Lakshmanan M Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2434229 Reviewed-by: automaticguardword Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Dinesh T Reviewed-by: Rajesh Devaraj Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/grmgr/grmgr.c | 16 ++++++++-------- drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c | 2 +- drivers/gpu/nvgpu/include/nvgpu/grmgr.h | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nvgpu/common/grmgr/grmgr.c b/drivers/gpu/nvgpu/common/grmgr/grmgr.c index 4a5744475..640ac9ada 100644 --- a/drivers/gpu/nvgpu/common/grmgr/grmgr.c +++ b/drivers/gpu/nvgpu/common/grmgr/grmgr.c @@ -483,9 +483,9 @@ u32 nvgpu_grmgr_get_gr_max_veid_count(struct gk20a *g, u32 gr_instance_id) return nvgpu_grmgr_get_max_veid_count(g, gpu_instance_id); } -u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id) +u32 nvgpu_grmgr_get_gr_logical_gpc_mask(struct gk20a *g, u32 gr_instance_id) { - u32 physical_gpc_mask = 0U; + u32 logical_gpc_mask = 0U; u32 gpc_indx; struct nvgpu_gpu_instance *gpu_instance; struct nvgpu_gr_syspipe *gr_syspipe; @@ -496,16 +496,16 @@ u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id) gr_syspipe = &gpu_instance->gr_syspipe; for (gpc_indx = 0U; gpc_indx < gr_syspipe->num_gpc; gpc_indx++) { - physical_gpc_mask |= BIT32( - gr_syspipe->gpcs[gpc_indx].physical_id); + logical_gpc_mask |= BIT32( + gr_syspipe->gpcs[gpc_indx].logical_id); nvgpu_log(g, gpu_dbg_mig, "gpu_instance_id[%u] gr_instance_id[%u] gpc_indx[%u] " - "physical_gpc_id[%u] physical_gpc_mask[%x]", + "logical_gpc_id[%u] logical_gpc_mask[%x]", gpu_instance_id, gr_instance_id, gpc_indx, - gr_syspipe->gpcs[gpc_indx].physical_id, - physical_gpc_mask); + gr_syspipe->gpcs[gpc_indx].logical_id, + logical_gpc_mask); } - return physical_gpc_mask; + return logical_gpc_mask; } diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c b/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c index 4f28ffcae..5f1e693f0 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c @@ -53,7 +53,7 @@ static u32 get_gpc_falcon_idx_mask(struct gk20a *g) u32 gpc_falcon_idx_mask = 0U; if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { - gpc_falcon_idx_mask = nvgpu_grmgr_get_gr_physical_gpc_mask(g, + gpc_falcon_idx_mask = nvgpu_grmgr_get_gr_logical_gpc_mask(g, nvgpu_gr_get_cur_instance_id(g)); } else { u32 gpc_fs_mask; diff --git a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h index 178b7c437..aa99e480c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h @@ -49,7 +49,7 @@ u32 nvgpu_grmgr_get_gr_instance_id_for_syspipe(struct gk20a *g, u32 nvgpu_grmgr_get_gpu_instance_max_veid_count(struct gk20a *g, u32 gpu_instance_id); u32 nvgpu_grmgr_get_gr_max_veid_count(struct gk20a *g, u32 gr_instance_id); -u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id); +u32 nvgpu_grmgr_get_gr_logical_gpc_mask(struct gk20a *g, u32 gr_instance_id); static inline bool nvgpu_grmgr_is_mig_type_gpu_instance( struct nvgpu_gpu_instance *gpu_instance)