diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100.h b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100.h index 83b986c88..2af55eae6 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100.h +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,22 +26,6 @@ struct gk20a; struct nvgpu_gr_config; -/* Copy required definitions from clc6c0.h class file */ -#define NVC6C0_SET_CB_BASE 0x0220U -#define NVC6C0_SET_BES_CROP_DEBUG4 0x022cU -#define NVC6C0_SET_TEX_IN_DBG 0x0238U -#define NVC6C0_SET_SKEDCHECK 0x023cU -#define NVC697_SET_SHADER_EXCEPTIONS 0x1528U -#define NVC6C0_SET_SHADER_EXCEPTIONS 0x1528U -#define NVC697_SET_CIRCULAR_BUFFER_SIZE 0x1280U -#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU - -/* - * Hardware divides sw_method enum value by 2 before passing as "offset". - * Left shift given offset by 2 to obtain sw_method enum value. - */ -#define NVGPU_GA100_SW_METHOD_SHIFT 2U - int ga100_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data); void ga100_gr_intr_enable_exceptions(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c index 69a0b888e..52e5f1cc4 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -119,43 +119,25 @@ u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g, int ga100_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data) { + int ret = -EINVAL; + nvgpu_log_fn(g, " "); #ifdef CONFIG_NVGPU_HAL_NON_FUSA - if (class_num == AMPERE_COMPUTE_A) { - switch (offset << NVGPU_GA100_SW_METHOD_SHIFT) { - case NVC6C0_SET_BES_CROP_DEBUG4: - g->ops.gr.set_bes_crop_debug4(g, data); - return 0; - case NVC6C0_SET_SHADER_EXCEPTIONS: - g->ops.gr.intr.set_shader_exceptions(g, data); - return 0; - case NVC6C0_SET_TEX_IN_DBG: - gv11b_gr_intr_set_tex_in_dbg(g, data); - return 0; - case NVC6C0_SET_SKEDCHECK: - gv11b_gr_intr_set_skedcheck(g, data); - return 0; - } + if (class_num == gr_compute_class_v()) { + ret = g->ops.gr.intr.handle_compute_sw_method(g, addr, class_num, + offset, data); } #endif #if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) - if (class_num == AMPERE_A) { - switch (offset << NVGPU_GA100_SW_METHOD_SHIFT) { - case NVC697_SET_SHADER_EXCEPTIONS: - g->ops.gr.intr.set_shader_exceptions(g, data); - return 0; - case NVC697_SET_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_circular_buffer_size(g, data); - return 0; - case NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_alpha_circular_buffer_size(g, data); - return 0; - } + if (class_num == gr_graphics_class_v()) { + ret = g->ops.gr.intr.handle_gfx_sw_method(g, addr, class_num, + offset, data); } #endif - return -EINVAL; + + return ret; } bool ga100_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception) diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h index 7ac0cd477..c6dab9b98 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -30,24 +30,16 @@ struct nvgpu_gr_sm_ecc_status; enum nvgpu_gr_sm_ecc_error_types; struct nvgpu_gr_intr_info; -/* Copy required definitions from clc797.h and clc7c0.h class files */ -#define NVC797_SET_SHADER_EXCEPTIONS 0x1528U -#define NVC797_SET_GO_IDLE_TIMEOUT 0x022cU -#define NVC797_SET_CIRCULAR_BUFFER_SIZE 0x1280U -#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU -#define NVC797_SET_CB_BASE 0x1014U -#define NVC797_SET_BES_CROP_DEBUG4 0x10b0U -#define NVC797_SET_TEX_IN_DBG 0x10bcU -#define NVC797_SET_SKEDCHECK 0x10c0U - -#define NVC7C0_SET_SHADER_EXCEPTIONS 0x1528U -#define NVC7C0_SET_CB_BASE 0x0220U -#define NVC7C0_SET_BES_CROP_DEBUG4 0x022cU -#define NVC7C0_SET_TEX_IN_DBG 0x0238U -#define NVC7C0_SET_SKEDCHECK 0x023cU - int ga10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data); +#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) +int ga10b_gr_intr_handle_gfx_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data); +#endif +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) +int ga10b_gr_intr_handle_compute_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data); +#endif void ga10b_gr_intr_enable_interrupts(struct gk20a *g, bool enable); void ga10b_gr_intr_enable_gpc_exceptions(struct gk20a *g, struct nvgpu_gr_config *gr_config); diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c index 8e5d50390..d0fbd38c2 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c @@ -103,17 +103,104 @@ u32 ga10b_gr_intr_enable_mask(struct gk20a *g) return gr_intr_en_mask(); } -int ga10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, - u32 class_num, u32 offset, u32 data) +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) +int ga10b_gr_intr_handle_compute_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data) { -#if defined(CONFIG_NVGPU_HAL_NON_FUSA) || (defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)) /* * Hardware divides sw_method enum value by 2 before passing as "offset". * Left shift given offset by 2 to obtain sw_method enum value. */ u32 left_shift_by_2 = 2U; + + (void)addr; + (void)class_num; + + nvgpu_log_fn(g, " "); + + switch (offset << left_shift_by_2) { + case gr_compute_method_set_shader_exceptions_v(): + g->ops.gr.intr.set_shader_exceptions(g, data); + return 0; + case gr_compute_method_set_cb_base_v(): + /* + * This method is only implemented for gm107 in resman + * code. However, this method has never been defined in + * nvgpu code. This case is added for debug purposes. + */ + nvgpu_err(g, "Unhandled set_cb_base method"); + return 0; + case gr_compute_method_set_bes_crop_debug4_v(): + g->ops.gr.set_bes_crop_debug4(g, data); + return 0; + case gr_compute_method_set_tex_in_dbg_v(): + gv11b_gr_intr_set_tex_in_dbg(g, data); + return 0; + case gr_compute_method_set_skedcheck_v(): + gv11b_gr_intr_set_skedcheck(g, data); + return 0; + } + + return -EINVAL; +} #endif +#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) +int ga10b_gr_intr_handle_gfx_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data) +{ + /* + * Hardware divides sw_method enum value by 2 before passing as "offset". + * Left shift given offset by 2 to obtain sw_method enum value. + */ + u32 left_shift_by_2 = 2U; + + (void)addr; + (void)class_num; + + nvgpu_log_fn(g, " "); + + switch (offset << left_shift_by_2) { + case gr_graphics_method_set_shader_exceptions_v(): + g->ops.gr.intr.set_shader_exceptions(g, data); + return 0; + case gr_graphics_method_set_go_idle_timeout_v(): + gp10b_gr_intr_set_go_idle_timeout(g, data); + return 0; + case gr_graphics_method_set_circular_buffer_size_v(): + g->ops.gr.set_circular_buffer_size(g, data); + return 0; + case gr_graphics_method_set_alpha_circular_buffer_size_v(): + g->ops.gr.set_alpha_circular_buffer_size(g, data); + return 0; + case gr_graphics_method_set_cb_base_v(): + /* + * This method is only implemented for gm107 in resman + * code. However, this method has never been defined in + * nvgpu code. This case is added for debug purposes. + */ + nvgpu_err(g, "Unhandled set_cb_base method"); + return 0; + case gr_graphics_method_set_bes_crop_debug4_v(): + g->ops.gr.set_bes_crop_debug4(g, data); + return 0; + case gr_graphics_method_set_tex_in_dbg_v(): + gv11b_gr_intr_set_tex_in_dbg(g, data); + return 0; + case gr_graphics_method_set_skedcheck_v(): + gv11b_gr_intr_set_skedcheck(g, data); + return 0; + } + + return -EINVAL; +} +#endif + +int ga10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data) +{ + int ret = -EINVAL; + (void)addr; (void)class_num; (void)offset; @@ -122,69 +209,20 @@ int ga10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, nvgpu_log_fn(g, " "); #ifdef CONFIG_NVGPU_HAL_NON_FUSA - if (class_num == AMPERE_COMPUTE_B) { - switch (offset << left_shift_by_2) { - case NVC7C0_SET_SHADER_EXCEPTIONS: - g->ops.gr.intr.set_shader_exceptions(g, data); - return 0; - case NVC7C0_SET_CB_BASE: - /* - * This method is only implemented for gm107 in resman - * code. However, this method has never been defined in - * nvgpu code. This case is added for debug purposes. - */ - nvgpu_err(g, "Unhandled set_cb_base method"); - return 0; - case NVC7C0_SET_BES_CROP_DEBUG4: - g->ops.gr.set_bes_crop_debug4(g, data); - return 0; - case NVC7C0_SET_TEX_IN_DBG: - gv11b_gr_intr_set_tex_in_dbg(g, data); - return 0; - case NVC7C0_SET_SKEDCHECK: - gv11b_gr_intr_set_skedcheck(g, data); - return 0; - } + if (class_num == gr_compute_class_v()) { + ret = g->ops.gr.intr.handle_compute_sw_method(g, addr, class_num, + offset, data); } #endif #if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) - if (class_num == AMPERE_B) { - switch (offset << left_shift_by_2) { - case NVC797_SET_SHADER_EXCEPTIONS: - g->ops.gr.intr.set_shader_exceptions(g, data); - return 0; - case NVC797_SET_GO_IDLE_TIMEOUT: - gp10b_gr_intr_set_go_idle_timeout(g, data); - return 0; - case NVC797_SET_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_circular_buffer_size(g, data); - return 0; - case NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_alpha_circular_buffer_size(g, data); - return 0; - case NVC797_SET_CB_BASE: - /* - * This method is only implemented for gm107 in resman - * code. However, this method has never been defined in - * nvgpu code. This case is added for debug purposes. - */ - nvgpu_err(g, "Unhandled set_cb_base method"); - return 0; - case NVC797_SET_BES_CROP_DEBUG4: - g->ops.gr.set_bes_crop_debug4(g, data); - return 0; - case NVC797_SET_TEX_IN_DBG: - gv11b_gr_intr_set_tex_in_dbg(g, data); - return 0; - case NVC797_SET_SKEDCHECK: - gv11b_gr_intr_set_skedcheck(g, data); - return 0; - } + if (class_num == gr_graphics_class_v()) { + ret = g->ops.gr.intr.handle_gfx_sw_method(g, addr, class_num, + offset, data); } #endif - return -EINVAL; + return ret; } static u32 ga10b_gr_intr_check_gr_mme_fe1_exception(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 878ae1d53..6d9cbe7fe 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -710,6 +710,12 @@ static const struct gops_gr_init ga100_ops_gr_init = { static const struct gops_gr_intr ga100_ops_gr_intr = { .handle_fecs_error = gv11b_gr_intr_handle_fecs_error, .handle_sw_method = ga100_gr_intr_handle_sw_method, +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) + .handle_compute_sw_method = ga10b_gr_intr_handle_compute_sw_method, +#endif +#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) + .handle_gfx_sw_method = ga10b_gr_intr_handle_gfx_sw_method, +#endif .handle_class_error = gp10b_gr_intr_handle_class_error, .clear_pending_interrupts = gm20b_gr_intr_clear_pending_interrupts, .read_pending_interrupts = ga100_gr_intr_read_pending_interrupts, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index d9b383c93..6be031793 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -710,6 +710,12 @@ static const struct gops_gr_init ga10b_ops_gr_init = { static const struct gops_gr_intr ga10b_ops_gr_intr = { .handle_fecs_error = gv11b_gr_intr_handle_fecs_error, .handle_sw_method = ga10b_gr_intr_handle_sw_method, +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) + .handle_compute_sw_method = ga10b_gr_intr_handle_compute_sw_method, +#endif +#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) + .handle_gfx_sw_method = ga10b_gr_intr_handle_gfx_sw_method, +#endif .handle_class_error = gp10b_gr_intr_handle_class_error, .clear_pending_interrupts = gm20b_gr_intr_clear_pending_interrupts, .read_pending_interrupts = ga10b_gr_intr_read_pending_interrupts, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index 731ad1f3f..0e8f6c178 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -508,6 +508,14 @@ struct gops_gr_intr { struct nvgpu_gr_isr_data *isr_data); int (*handle_sw_method)(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data); +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) + int (*handle_compute_sw_method)(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data); +#endif +#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) + int (*handle_gfx_sw_method)(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data); +#endif void (*set_shader_exceptions)(struct gk20a *g, u32 data); void (*handle_class_error)(struct gk20a *g, u32 chid, diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h index 65c53d9e7..8b8d90c9e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1269,4 +1269,20 @@ (0x100000U) #define gr_gpcs_pri_tpcs_sm_sch_macro_sched_exit_wait_for_errbar_disabled_f()\ (0x0U) +#define gr_graphics_class_v() (0x0000c697U) +#define gr_graphics_method_set_shader_exceptions_v() (0x00001528U) +#define gr_graphics_method_set_shader_exceptions_enable_false_v() (0x00000000U) +#define gr_graphics_method_set_go_idle_timeout_v() (0x0000022cU) +#define gr_graphics_method_set_circular_buffer_size_v() (0x00001280U) +#define gr_graphics_method_set_alpha_circular_buffer_size_v() (0x000002dcU) +#define gr_graphics_method_set_cb_base_v() (0x00001014U) +#define gr_graphics_method_set_bes_crop_debug4_v() (0x000010b0U) +#define gr_graphics_method_set_tex_in_dbg_v() (0x000010bcU) +#define gr_graphics_method_set_skedcheck_v() (0x000010c0U) +#define gr_compute_class_v() (0x0000c6c0U) +#define gr_compute_method_set_shader_exceptions_v() (0x00001528U) +#define gr_compute_method_set_cb_base_v() (0x00000220U) +#define gr_compute_method_set_bes_crop_debug4_v() (0x0000022cU) +#define gr_compute_method_set_tex_in_dbg_v() (0x00000238U) +#define gr_compute_method_set_skedcheck_v() (0x0000023cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h index 3e2440822..9bce8d730 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h @@ -1270,4 +1270,20 @@ (0x100000U) #define gr_gpcs_pri_tpcs_sm_sch_macro_sched_exit_wait_for_errbar_disabled_f()\ (0x0U) +#define gr_graphics_class_v() (0x0000c797U) +#define gr_graphics_method_set_shader_exceptions_v() (0x00001528U) +#define gr_graphics_method_set_shader_exceptions_enable_false_v() (0x00000000U) +#define gr_graphics_method_set_go_idle_timeout_v() (0x0000022cU) +#define gr_graphics_method_set_circular_buffer_size_v() (0x00001280U) +#define gr_graphics_method_set_alpha_circular_buffer_size_v() (0x000002dcU) +#define gr_graphics_method_set_cb_base_v() (0x00001014U) +#define gr_graphics_method_set_bes_crop_debug4_v() (0x000010b0U) +#define gr_graphics_method_set_tex_in_dbg_v() (0x000010bcU) +#define gr_graphics_method_set_skedcheck_v() (0x000010c0U) +#define gr_compute_class_v() (0x0000c7c0U) +#define gr_compute_method_set_shader_exceptions_v() (0x00001528U) +#define gr_compute_method_set_cb_base_v() (0x00000220U) +#define gr_compute_method_set_bes_crop_debug4_v() (0x0000022cU) +#define gr_compute_method_set_tex_in_dbg_v() (0x00000238U) +#define gr_compute_method_set_skedcheck_v() (0x0000023cU) #endif