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gpu: nvgpu: remove circular dependency between gr and fifo

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channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.

Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);

JIRA NVGPU-3214

Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-04-30 20:30:43 -07:00
committed by mobile promotions
parent 7581601f80
commit 57be9a09fd
16 changed files with 111 additions and 39 deletions
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68
drivers/gpu/nvgpu/common/gr/gr_intr.c
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@@ -236,7 +236,7 @@ struct channel_gk20a *nvgpu_gr_intr_get_channel_from_ctx(struct gk20a *g,
u32 curr_ctx, u32 *curr_tsgid)
{
struct fifo_gk20a *f = &g->fifo;
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr_intr *intr = g->gr->intr;
u32 chid;
u32 tsgid = NVGPU_INVALID_TSG_ID;
u32 i;
@@ -248,13 +248,13 @@ struct channel_gk20a *nvgpu_gr_intr_get_channel_from_ctx(struct gk20a *g,
* unloaded. No need to check ctx_valid bit
*/
nvgpu_spinlock_acquire(&gr->ch_tlb_lock);
nvgpu_spinlock_acquire(&intr->ch_tlb_lock);
/* check cache first */
for (i = 0; i < GR_CHANNEL_MAP_TLB_SIZE; i++) {
if (gr->chid_tlb[i].curr_ctx == curr_ctx) {
chid = gr->chid_tlb[i].chid;
tsgid = gr->chid_tlb[i].tsgid;
if (intr->chid_tlb[i].curr_ctx == curr_ctx) {
chid = intr->chid_tlb[i].chid;
tsgid = intr->chid_tlb[i].tsgid;
ret_ch = gk20a_channel_from_id(g, chid);
goto unlock;
}
@@ -284,25 +284,25 @@ struct channel_gk20a *nvgpu_gr_intr_get_channel_from_ctx(struct gk20a *g,
/* add to free tlb entry */
for (i = 0; i < GR_CHANNEL_MAP_TLB_SIZE; i++) {
if (gr->chid_tlb[i].curr_ctx == 0U) {
gr->chid_tlb[i].curr_ctx = curr_ctx;
gr->chid_tlb[i].chid = chid;
gr->chid_tlb[i].tsgid = tsgid;
if (intr->chid_tlb[i].curr_ctx == 0U) {
intr->chid_tlb[i].curr_ctx = curr_ctx;
intr->chid_tlb[i].chid = chid;
intr->chid_tlb[i].tsgid = tsgid;
goto unlock;
}
}
/* no free entry, flush one */
gr->chid_tlb[gr->channel_tlb_flush_index].curr_ctx = curr_ctx;
gr->chid_tlb[gr->channel_tlb_flush_index].chid = chid;
gr->chid_tlb[gr->channel_tlb_flush_index].tsgid = tsgid;
intr->chid_tlb[intr->channel_tlb_flush_index].curr_ctx = curr_ctx;
intr->chid_tlb[intr->channel_tlb_flush_index].chid = chid;
intr->chid_tlb[intr->channel_tlb_flush_index].tsgid = tsgid;
gr->channel_tlb_flush_index =
(gr->channel_tlb_flush_index + 1U) &
intr->channel_tlb_flush_index =
(intr->channel_tlb_flush_index + 1U) &
(GR_CHANNEL_MAP_TLB_SIZE - 1U);
unlock:
nvgpu_spinlock_release(&gr->ch_tlb_lock);
nvgpu_spinlock_release(&intr->ch_tlb_lock);
if (curr_tsgid != NULL) {
*curr_tsgid = tsgid;
}
@@ -864,3 +864,41 @@ int nvgpu_gr_intr_stall_isr(struct gk20a *g)
return 0;
}
/* invalidate channel lookup tlb */
void nvgpu_gr_intr_flush_channel_tlb(struct gk20a *g)
{
struct nvgpu_gr_intr *intr = g->gr->intr;
nvgpu_spinlock_acquire(&intr->ch_tlb_lock);
(void) memset(intr->chid_tlb, 0,
sizeof(struct gr_channel_map_tlb_entry) *
GR_CHANNEL_MAP_TLB_SIZE);
nvgpu_spinlock_release(&intr->ch_tlb_lock);
}
struct nvgpu_gr_intr *nvgpu_gr_intr_init_support(struct gk20a *g)
{
struct nvgpu_gr_intr *intr;
nvgpu_log_fn(g, " ");
intr = nvgpu_kzalloc(g, sizeof(*intr));
if (intr == NULL) {
return intr;
}
nvgpu_spinlock_init(&intr->ch_tlb_lock);
return intr;
}
void nvgpu_gr_intr_remove_support(struct gk20a *g, struct nvgpu_gr_intr *intr)
{
nvgpu_log_fn(g, " ");
if (intr == NULL) {
return;
}
nvgpu_kfree(g, intr);
}