diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index fa7745667..9ba6f49a0 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu @@ -153,7 +153,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ vgpu/fifo_vgpu.o \ vgpu/ce2_vgpu.o \ vgpu/mm_vgpu.o \ - vgpu/debug_vgpu.o \ vgpu/vgpu.o \ vgpu/dbg_vgpu.o \ vgpu/fecs_trace_vgpu.o \ @@ -245,8 +244,7 @@ nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gp10b_tegra.o nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ vgpu/gp10b/vgpu_hal_gp10b.o \ vgpu/gp10b/vgpu_gr_gp10b.o \ - vgpu/gp10b/vgpu_mm_gp10b.o \ - vgpu/gp10b/vgpu_fifo_gp10b.o + vgpu/gp10b/vgpu_mm_gp10b.o endif ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 76c87c00a..39d05978c 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -71,7 +71,7 @@ #define PRIV_SECURITY_DISABLE 0x01 -static int gm20b_get_litter_value(struct gk20a *g, int value) +int gm20b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; switch (value) { diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.h b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h index 1e149ce28..22eae1824 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h @@ -1,7 +1,7 @@ /* * GM20B Graphics * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,4 +27,5 @@ struct gk20a; int gm20b_init_hal(struct gk20a *g); +int gm20b_get_litter_value(struct gk20a *g, int value); #endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index f298f26c8..61284225a 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -80,7 +80,7 @@ #include #include -static int gp10b_get_litter_value(struct gk20a *g, int value) +int gp10b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; switch (value) { diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h index f29248092..cf3c295d3 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,4 +27,5 @@ struct gk20a; int gp10b_init_hal(struct gk20a *gops); +int gp10b_get_litter_value(struct gk20a *g, int value); #endif diff --git a/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c index e53a3c184..bd225f0ca 100644 --- a/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c @@ -43,14 +43,9 @@ int vgpu_ce2_nonstall_isr(struct gk20a *g, return 0; } -static u32 vgpu_ce_get_num_pce(struct gk20a *g) +u32 vgpu_ce_get_num_pce(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); return priv->constants.num_pce; } - -void vgpu_init_ce2_ops(struct gpu_ops *gops) -{ - gops->ce2.get_num_pce = vgpu_ce_get_num_pce; -} diff --git a/drivers/gpu/nvgpu/vgpu/css_vgpu.c b/drivers/gpu/nvgpu/vgpu/css_vgpu.c index 0b3c6a259..bcb01fac2 100644 --- a/drivers/gpu/nvgpu/vgpu/css_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/css_vgpu.c @@ -29,6 +29,7 @@ #include "gk20a/platform_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "vgpu.h" +#include "css_vgpu.h" static struct tegra_hv_ivm_cookie *css_cookie; @@ -93,7 +94,7 @@ fail: return err; } -static void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr) +void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr) { struct gk20a_cs_snapshot *data = gr->cs_data; @@ -108,7 +109,7 @@ static void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr) gk20a_dbg_info("cyclestats(vgpu): buffer for snapshots released\n"); } -static int vgpu_css_flush_snapshots(struct channel_gk20a *ch, +int vgpu_css_flush_snapshots(struct channel_gk20a *ch, u32 *pending, bool *hw_overflow) { struct gk20a *g = ch->g; @@ -164,7 +165,7 @@ static int vgpu_css_attach(struct channel_gk20a *ch, return err; } -static int vgpu_css_detach(struct channel_gk20a *ch, +int vgpu_css_detach(struct channel_gk20a *ch, struct gk20a_cs_snapshot_client *cs_client) { struct gk20a *g = ch->g; @@ -190,7 +191,7 @@ static int vgpu_css_detach(struct channel_gk20a *ch, return err; } -static int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch, +int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch, struct gk20a_cs_snapshot_client *cs_client) { int ret; @@ -202,17 +203,4 @@ static int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch, ret = vgpu_css_init_snapshot_buffer(&ch->g->gr); return ret; } - -void vgpu_init_css_ops(struct gpu_ops *gops) -{ - gops->css.enable_snapshot = vgpu_css_enable_snapshot_buffer; - gops->css.disable_snapshot = vgpu_css_release_snapshot_buffer; - gops->css.check_data_available = vgpu_css_flush_snapshots; - gops->css.detach_snapshot = vgpu_css_detach; - - /* Following entries are not used when virtual, NULL them */ - gops->css.set_handled_snapshots = NULL; - gops->css.allocate_perfmon_ids = NULL; - gops->css.release_perfmon_ids = NULL; -} #endif /* CONFIG_GK20A_CYCLE_STATS */ diff --git a/drivers/gpu/nvgpu/vgpu/debug_vgpu.c b/drivers/gpu/nvgpu/vgpu/css_vgpu.h similarity index 65% rename from drivers/gpu/nvgpu/vgpu/debug_vgpu.c rename to drivers/gpu/nvgpu/vgpu/css_vgpu.h index cb858c22c..b61c9862e 100644 --- a/drivers/gpu/nvgpu/vgpu/debug_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/css_vgpu.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,14 +20,21 @@ * DEALINGS IN THE SOFTWARE. */ -#include "vgpu/vgpu.h" +#ifndef _CSS_VGPU_H_ +#define _CSS_VGPU_H_ -static void vgpu_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o) -{ - /* debug dump not supported */ -} +#include -void vgpu_init_debug_ops(struct gpu_ops *gops) -{ - gops->debug.show_dump = vgpu_debug_show_dump; -} +struct gr_gk20a; +struct channel_gk20a; +struct gk20a_cs_snapshot_client; + +void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr); +int vgpu_css_flush_snapshots(struct channel_gk20a *ch, + u32 *pending, bool *hw_overflow); +int vgpu_css_detach(struct channel_gk20a *ch, + struct gk20a_cs_snapshot_client *cs_client); +int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch, + struct gk20a_cs_snapshot_client *cs_client); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c index 416b89035..6e8ab561a 100644 --- a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c @@ -27,10 +27,11 @@ #include "gk20a/channel_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "vgpu.h" +#include "dbg_vgpu.h" #include -static int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, +int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, struct nvgpu_dbg_gpu_reg_op *ops, u64 num_ops) { @@ -76,7 +77,7 @@ fail: return err; } -static int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, __u32 mode) +int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, __u32 mode) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_set_powergate_params *p = &msg.params.set_powergate; @@ -124,7 +125,7 @@ static int vgpu_sendrecv_prof_cmd(struct dbg_session_gk20a *dbg_s, u32 mode) return err; } -static bool vgpu_check_and_set_global_reservation( +bool vgpu_check_and_set_global_reservation( struct dbg_session_gk20a *dbg_s, struct dbg_profiler_object_data *prof_obj) { @@ -144,7 +145,7 @@ static bool vgpu_check_and_set_global_reservation( return false; } -static bool vgpu_check_and_set_context_reservation( +bool vgpu_check_and_set_context_reservation( struct dbg_session_gk20a *dbg_s, struct dbg_profiler_object_data *prof_obj) { @@ -167,7 +168,7 @@ static bool vgpu_check_and_set_context_reservation( return false; } -static void vgpu_release_profiler_reservation( +void vgpu_release_profiler_reservation( struct dbg_session_gk20a *dbg_s, struct dbg_profiler_object_data *prof_obj) { @@ -205,26 +206,12 @@ static int vgpu_sendrecv_perfbuf_cmd(struct gk20a *g, u64 offset, u32 size) return err; } -static int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size) +int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size) { return vgpu_sendrecv_perfbuf_cmd(g, offset, size); } -static int vgpu_perfbuffer_disable(struct gk20a *g) +int vgpu_perfbuffer_disable(struct gk20a *g) { return vgpu_sendrecv_perfbuf_cmd(g, 0, 0); } - -void vgpu_init_dbg_session_ops(struct gpu_ops *gops) -{ - gops->dbg_session_ops.exec_reg_ops = vgpu_exec_regops; - gops->dbg_session_ops.dbg_set_powergate = vgpu_dbg_set_powergate; - gops->dbg_session_ops.check_and_set_global_reservation = - vgpu_check_and_set_global_reservation; - gops->dbg_session_ops.check_and_set_context_reservation = - vgpu_check_and_set_context_reservation; - gops->dbg_session_ops.release_profiler_reservation = - vgpu_release_profiler_reservation; - gops->dbg_session_ops.perfbuffer_enable = vgpu_perfbuffer_enable; - gops->dbg_session_ops.perfbuffer_disable = vgpu_perfbuffer_disable; -} diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h new file mode 100644 index 000000000..fcdea931b --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DBG_VGPU_H_ +#define _DBG_VGPU_H_ + +struct dbg_session_gk20a; +struct nvgpu_dbg_gpu_reg_op; +struct dbg_profiler_object_data; +struct gk20a; + +int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, + struct nvgpu_dbg_gpu_reg_op *ops, + u64 num_ops); +int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, __u32 mode); +bool vgpu_check_and_set_global_reservation( + struct dbg_session_gk20a *dbg_s, + struct dbg_profiler_object_data *prof_obj); +bool vgpu_check_and_set_context_reservation( + struct dbg_session_gk20a *dbg_s, + struct dbg_profiler_object_data *prof_obj); + +void vgpu_release_profiler_reservation( + struct dbg_session_gk20a *dbg_s, + struct dbg_profiler_object_data *prof_obj); +int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size); +int vgpu_perfbuffer_disable(struct gk20a *g); +#endif diff --git a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c index 84de9d0bc..762cc10ad 100644 --- a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c @@ -41,7 +41,7 @@ struct vgpu_fecs_trace { void *buf; }; -static int vgpu_fecs_trace_init(struct gk20a *g) +int vgpu_fecs_trace_init(struct gk20a *g) { struct device *dev = dev_from_gk20a(g); struct device_node *np = dev->of_node; @@ -102,7 +102,7 @@ fail: return err; } -static int vgpu_fecs_trace_deinit(struct gk20a *g) +int vgpu_fecs_trace_deinit(struct gk20a *g) { struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; @@ -112,7 +112,7 @@ static int vgpu_fecs_trace_deinit(struct gk20a *g) return 0; } -static int vgpu_fecs_trace_enable(struct gk20a *g) +int vgpu_fecs_trace_enable(struct gk20a *g) { struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; struct tegra_vgpu_cmd_msg msg = { @@ -128,7 +128,7 @@ static int vgpu_fecs_trace_enable(struct gk20a *g) return err; } -static int vgpu_fecs_trace_disable(struct gk20a *g) +int vgpu_fecs_trace_disable(struct gk20a *g) { struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; struct tegra_vgpu_cmd_msg msg = { @@ -144,14 +144,14 @@ static int vgpu_fecs_trace_disable(struct gk20a *g) return err; } -static bool vpgpu_fecs_trace_is_enabled(struct gk20a *g) +bool vgpu_fecs_trace_is_enabled(struct gk20a *g) { struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; return (vcst && vcst->enabled); } -static int vgpu_fecs_trace_poll(struct gk20a *g) +int vgpu_fecs_trace_poll(struct gk20a *g) { struct tegra_vgpu_cmd_msg msg = { .cmd = TEGRA_VGPU_CMD_FECS_TRACE_POLL, @@ -165,7 +165,7 @@ static int vgpu_fecs_trace_poll(struct gk20a *g) return err; } -static int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size) +int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size) { struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; @@ -174,12 +174,12 @@ static int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size) return 0; } -static int vgpu_free_user_buffer(struct gk20a *g) +int vgpu_free_user_buffer(struct gk20a *g) { return 0; } -static int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma) +int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma) { struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; unsigned long size = vcst->cookie->size; @@ -194,7 +194,7 @@ static int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma) vma->vm_page_prot); } -static int vgpu_fecs_trace_max_entries(struct gk20a *g, +int vgpu_fecs_trace_max_entries(struct gk20a *g, struct nvgpu_ctxsw_trace_filter *filter) { struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; @@ -206,7 +206,7 @@ static int vgpu_fecs_trace_max_entries(struct gk20a *g, #error "FECS trace filter size mismatch!" #endif -static int vgpu_fecs_trace_set_filter(struct gk20a *g, +int vgpu_fecs_trace_set_filter(struct gk20a *g, struct nvgpu_ctxsw_trace_filter *filter) { struct tegra_vgpu_cmd_msg msg = { @@ -223,25 +223,6 @@ static int vgpu_fecs_trace_set_filter(struct gk20a *g, return err; } -void vgpu_init_fecs_trace_ops(struct gpu_ops *ops) -{ - ops->fecs_trace.init = vgpu_fecs_trace_init; - ops->fecs_trace.deinit = vgpu_fecs_trace_deinit; - ops->fecs_trace.enable = vgpu_fecs_trace_enable; - ops->fecs_trace.disable = vgpu_fecs_trace_disable; - ops->fecs_trace.is_enabled = vpgpu_fecs_trace_is_enabled; - ops->fecs_trace.reset = NULL; - ops->fecs_trace.flush = NULL; - ops->fecs_trace.poll = vgpu_fecs_trace_poll; - ops->fecs_trace.bind_channel = NULL; - ops->fecs_trace.unbind_channel = NULL; - ops->fecs_trace.max_entries = vgpu_fecs_trace_max_entries; - ops->fecs_trace.alloc_user_buffer = vgpu_alloc_user_buffer; - ops->fecs_trace.free_user_buffer = vgpu_free_user_buffer; - ops->fecs_trace.mmap_user_buffer = vgpu_mmap_user_buffer; - ops->fecs_trace.set_filter = vgpu_fecs_trace_set_filter; -} - void vgpu_fecs_trace_data_update(struct gk20a *g) { gk20a_ctxsw_trace_wake_up(g, 0); diff --git a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.h b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.h index d20de773b..392b344cc 100644 --- a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,8 +23,25 @@ #ifndef __FECS_TRACE_VGPU_H #define __FECS_TRACE_VGPU_H -struct gpu_ops; -void vgpu_init_fecs_trace_ops(struct gpu_ops *ops); +#include + +struct gk20a; +struct vm_area_struct; +struct nvgpu_ctxsw_trace_filter; + void vgpu_fecs_trace_data_update(struct gk20a *g); +int vgpu_fecs_trace_init(struct gk20a *g); +int vgpu_fecs_trace_deinit(struct gk20a *g); +int vgpu_fecs_trace_enable(struct gk20a *g); +int vgpu_fecs_trace_disable(struct gk20a *g); +bool vgpu_fecs_trace_is_enabled(struct gk20a *g); +int vgpu_fecs_trace_poll(struct gk20a *g); +int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size); +int vgpu_free_user_buffer(struct gk20a *g); +int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma); +int vgpu_fecs_trace_max_entries(struct gk20a *g, + struct nvgpu_ctxsw_trace_filter *filter); +int vgpu_fecs_trace_set_filter(struct gk20a *g, + struct nvgpu_ctxsw_trace_filter *filter); #endif /* __FECS_TRACE_VGPU_H */ diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 73a67d91d..582894b9a 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c @@ -32,12 +32,13 @@ #include #include "vgpu/vgpu.h" +#include "vgpu/fifo_vgpu.h" #include "gk20a/ctxsw_trace_gk20a.h" #include #include -static void vgpu_channel_bind(struct channel_gk20a *ch) +void vgpu_channel_bind(struct channel_gk20a *ch) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_channel_config_params *p = @@ -56,7 +57,7 @@ static void vgpu_channel_bind(struct channel_gk20a *ch) nvgpu_atomic_set(&ch->bound, true); } -static void vgpu_channel_unbind(struct channel_gk20a *ch) +void vgpu_channel_unbind(struct channel_gk20a *ch) { gk20a_dbg_fn(""); @@ -76,7 +77,7 @@ static void vgpu_channel_unbind(struct channel_gk20a *ch) } -static int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) +int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx; @@ -99,7 +100,7 @@ static int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) return 0; } -static void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch) +void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx; @@ -114,7 +115,7 @@ static void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch) WARN_ON(err || msg.ret); } -static void vgpu_channel_enable(struct channel_gk20a *ch) +void vgpu_channel_enable(struct channel_gk20a *ch) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_channel_config_params *p = @@ -130,7 +131,7 @@ static void vgpu_channel_enable(struct channel_gk20a *ch) WARN_ON(err || msg.ret); } -static void vgpu_channel_disable(struct channel_gk20a *ch) +void vgpu_channel_disable(struct channel_gk20a *ch) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_channel_config_params *p = @@ -146,7 +147,7 @@ static void vgpu_channel_disable(struct channel_gk20a *ch) WARN_ON(err || msg.ret); } -static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, +int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, u32 gpfifo_entries, unsigned long acquire_timeout, u32 flags) { @@ -170,7 +171,7 @@ static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, return (err || msg.ret) ? -ENOMEM : 0; } -static int vgpu_fifo_init_engine_info(struct fifo_gk20a *f) +int vgpu_fifo_init_engine_info(struct fifo_gk20a *f) { struct vgpu_priv_data *priv = vgpu_get_priv_data(f->g); struct tegra_vgpu_engines_info *engines = &priv->constants.engines_info; @@ -377,7 +378,7 @@ clean_up: return err; } -static int vgpu_init_fifo_setup_hw(struct gk20a *g) +int vgpu_init_fifo_setup_hw(struct gk20a *g) { gk20a_dbg_fn(""); @@ -440,7 +441,7 @@ int vgpu_init_fifo_support(struct gk20a *g) return err; } -static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid) +int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid) { struct fifo_gk20a *f = &g->fifo; struct channel_gk20a *ch = &f->channel[chid]; @@ -468,7 +469,7 @@ static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid) return err; } -static int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) +int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_tsg_preempt_params *p = @@ -579,7 +580,7 @@ static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, special cases below: runlist->active_channels will NOT be changed. (chid == ~0 && !add) means remove all active channels from runlist. (chid == ~0 && add) means restore all active channels on runlist. */ -static int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, +int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, u32 chid, bool add, bool wait_for_finish) { struct fifo_runlist_info_gk20a *runlist = NULL; @@ -599,14 +600,14 @@ static int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, return ret; } -static int vgpu_fifo_wait_engine_idle(struct gk20a *g) +int vgpu_fifo_wait_engine_idle(struct gk20a *g) { gk20a_dbg_fn(""); return 0; } -static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) +int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_channel_priority_params *p = @@ -646,7 +647,7 @@ static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, return err ? err : msg.ret; } -static int vgpu_fifo_set_runlist_interleave(struct gk20a *g, +int vgpu_fifo_set_runlist_interleave(struct gk20a *g, u32 id, bool is_tsg, u32 runlist_id, @@ -674,7 +675,7 @@ static int vgpu_fifo_set_runlist_interleave(struct gk20a *g, return err ? err : msg.ret; } -static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) +int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_channel_timeslice_params *p = @@ -695,7 +696,7 @@ static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) return err; } -static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, +int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, u32 err_code, bool verbose) { struct tsg_gk20a *tsg = NULL; @@ -818,29 +819,3 @@ u32 vgpu_fifo_default_timeslice_us(struct gk20a *g) return priv->constants.default_timeslice_us; } - -void vgpu_init_fifo_ops(struct gpu_ops *gops) -{ - gops->fifo.init_fifo_setup_hw = vgpu_init_fifo_setup_hw; - gops->fifo.bind_channel = vgpu_channel_bind; - gops->fifo.unbind_channel = vgpu_channel_unbind; - gops->fifo.enable_channel = vgpu_channel_enable; - gops->fifo.disable_channel = vgpu_channel_disable; - gops->fifo.alloc_inst = vgpu_channel_alloc_inst; - gops->fifo.free_inst = vgpu_channel_free_inst; - gops->fifo.setup_ramfc = vgpu_channel_setup_ramfc; - gops->fifo.preempt_channel = vgpu_fifo_preempt_channel; - gops->fifo.preempt_tsg = vgpu_fifo_preempt_tsg; - gops->fifo.enable_tsg = gk20a_enable_tsg; - gops->fifo.disable_tsg = gk20a_disable_tsg; - /* Not supported yet for vgpu */ - gops->fifo.tsg_verify_channel_status = NULL; - gops->fifo.update_runlist = vgpu_fifo_update_runlist; - gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; - gops->fifo.channel_set_priority = vgpu_channel_set_priority; - gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; - gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; - gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch; - gops->fifo.init_engine_info = vgpu_fifo_init_engine_info; - gops->fifo.default_timeslice_us = vgpu_fifo_default_timeslice_us; -} diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h new file mode 100644 index 000000000..c5a51f97b --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FIFO_VGPU_H_ +#define _FIFO_VGPU_H_ + +#include + +struct gk20a; +struct channel_gk20a; +struct fifo_gk20a; +struct tsg_gk20a; + +int vgpu_init_fifo_setup_hw(struct gk20a *g); +void vgpu_channel_bind(struct channel_gk20a *ch); +void vgpu_channel_unbind(struct channel_gk20a *ch); +int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); +void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch); +void vgpu_channel_enable(struct channel_gk20a *ch); +void vgpu_channel_disable(struct channel_gk20a *ch); +int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, + u32 gpfifo_entries, + unsigned long acquire_timeout, u32 flags); +int vgpu_fifo_init_engine_info(struct fifo_gk20a *f); +int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid); +int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); +int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, + u32 chid, bool add, bool wait_for_finish); +int vgpu_fifo_wait_engine_idle(struct gk20a *g); +int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority); +int vgpu_fifo_set_runlist_interleave(struct gk20a *g, + u32 id, + bool is_tsg, + u32 runlist_id, + u32 new_level); +int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice); +int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, + u32 err_code, bool verbose); +u32 vgpu_fifo_default_timeslice_us(struct gk20a *g); +int vgpu_tsg_open(struct tsg_gk20a *tsg); +int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, + struct channel_gk20a *ch); +int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); +int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c index 0acafa8ea..06962a86b 100644 --- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c +++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,7 +23,7 @@ #include "gk20a/gk20a.h" #include "vgpu_gr_gm20b.h" -static int vgpu_gm20b_init_fs_state(struct gk20a *g) +int vgpu_gm20b_init_fs_state(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; u32 tpc_index, gpc_index; @@ -44,8 +44,3 @@ static int vgpu_gm20b_init_fs_state(struct gk20a *g) gr->no_of_sm = sm_id; return 0; } - -void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops) -{ - gops->gr.init_fs_state = vgpu_gm20b_init_fs_state; -} diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h index dda0de7b1..993a8f3da 100644 --- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h +++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,6 @@ #include "gk20a/gk20a.h" -void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops); +int vgpu_gm20b_init_fs_state(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c index 348510df3..618c80f85 100644 --- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -22,17 +22,582 @@ #include "gm20b/hal_gm20b.h" #include "vgpu/vgpu.h" +#include "vgpu/fifo_vgpu.h" +#include "vgpu/gr_vgpu.h" +#include "vgpu/ltc_vgpu.h" +#include "vgpu/mm_vgpu.h" +#include "vgpu/dbg_vgpu.h" +#include "vgpu/fecs_trace_vgpu.h" +#include "vgpu/css_vgpu.h" #include "vgpu_gr_gm20b.h" +#include "gk20a/bus_gk20a.h" +#include "gk20a/flcn_gk20a.h" +#include "gk20a/mc_gk20a.h" +#include "gk20a/fb_gk20a.h" + +#include "gm20b/gr_gm20b.h" +#include "gm20b/fifo_gm20b.h" +#include "gm20b/acr_gm20b.h" +#include "gm20b/pmu_gm20b.h" +#include "gm20b/fb_gm20b.h" +#include "gm20b/bus_gm20b.h" +#include "gm20b/cde_gm20b.h" +#include "gm20b/regops_gm20b.h" +#include "gm20b/clk_gm20b.h" +#include "gm20b/therm_gm20b.h" +#include "gm20b/mm_gm20b.h" +#include "gm20b/gr_ctx_gm20b.h" +#include "gm20b/gm20b_gating_reglist.h" +#include "gm20b/ltc_gm20b.h" + +#include + +#include +#include +#include +#include + +static const struct gpu_ops vgpu_gm20b_ops = { + .ltc = { + .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = gm20b_ltc_init_cbc, + .init_fs_state = vgpu_ltc_init_fs_state, + .init_comptags = vgpu_ltc_init_comptags, + .cbc_ctrl = NULL, + .isr = gm20b_ltc_isr, + .cbc_fix_config = gm20b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, + .set_enabled = gm20b_ltc_set_enabled, + }, + .ce2 = { + .isr_stall = gk20a_ce2_isr, + .isr_nonstall = gk20a_ce2_nonstall_isr, + .get_num_pce = vgpu_ce_get_num_pce, + }, + .gr = { + .init_gpc_mmu = gr_gm20b_init_gpc_mmu, + .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, + .cb_size_default = gr_gm20b_cb_size_default, + .calc_global_ctx_buffer_size = + gr_gm20b_calc_global_ctx_buffer_size, + .commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb, + .commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb, + .commit_global_cb_manager = gr_gm20b_commit_global_cb_manager, + .commit_global_pagepool = gr_gm20b_commit_global_pagepool, + .handle_sw_method = gr_gm20b_handle_sw_method, + .set_alpha_circular_buffer_size = + gr_gm20b_set_alpha_circular_buffer_size, + .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size, + .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions, + .is_valid_class = gr_gm20b_is_valid_class, + .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class, + .is_valid_compute_class = gr_gm20b_is_valid_compute_class, + .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, + .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, + .init_fs_state = vgpu_gm20b_init_fs_state, + .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, + .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, + .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, + .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask, + .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, + .free_channel_ctx = vgpu_gr_free_channel_ctx, + .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, + .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, + .get_zcull_info = vgpu_gr_get_zcull_info, + .is_tpc_addr = gr_gm20b_is_tpc_addr, + .get_tpc_num = gr_gm20b_get_tpc_num, + .detect_sm_arch = vgpu_gr_detect_sm_arch, + .add_zbc_color = gr_gk20a_add_zbc_color, + .add_zbc_depth = gr_gk20a_add_zbc_depth, + .zbc_set_table = vgpu_gr_add_zbc, + .zbc_query_table = vgpu_gr_query_zbc, + .pmu_save_zbc = gk20a_pmu_save_zbc, + .add_zbc = gr_gk20a_add_zbc, + .pagepool_default_size = gr_gm20b_pagepool_default_size, + .init_ctx_state = vgpu_gr_init_ctx_state, + .alloc_gr_ctx = vgpu_gr_alloc_gr_ctx, + .free_gr_ctx = vgpu_gr_free_gr_ctx, + .update_ctxsw_preemption_mode = + gr_gm20b_update_ctxsw_preemption_mode, + .dump_gr_regs = NULL, + .update_pc_sampling = gr_gm20b_update_pc_sampling, + .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, + .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, + .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, + .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, + .get_max_fbps_count = vgpu_gr_get_max_fbps_count, + .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, + .wait_empty = gr_gk20a_wait_idle, + .init_cyclestats = gr_gm20b_init_cyclestats, + .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, + .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, + .bpt_reg_info = gr_gm20b_bpt_reg_info, + .get_access_map = gr_gm20b_get_access_map, + .handle_fecs_error = gk20a_gr_handle_fecs_error, + .handle_sm_exception = gr_gk20a_handle_sm_exception, + .handle_tex_exception = gr_gk20a_handle_tex_exception, + .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions, + .enable_exceptions = gk20a_gr_enable_exceptions, + .get_lrf_tex_ltc_dram_override = NULL, + .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, + .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, + .record_sm_error_state = gm20b_gr_record_sm_error_state, + .update_sm_error_state = gm20b_gr_update_sm_error_state, + .clear_sm_error_state = vgpu_gr_clear_sm_error_state, + .suspend_contexts = vgpu_gr_suspend_contexts, + .resume_contexts = vgpu_gr_resume_contexts, + .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags, + .fuse_override = gm20b_gr_fuse_override, + .init_sm_id_table = gr_gk20a_init_sm_id_table, + .load_smid_config = gr_gm20b_load_smid_config, + .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, + .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, + .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, + .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, + .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, + .setup_rop_mapping = gr_gk20a_setup_rop_mapping, + .program_zcull_mapping = gr_gk20a_program_zcull_mapping, + .commit_global_timeslice = gr_gk20a_commit_global_timeslice, + .commit_inst = vgpu_gr_commit_inst, + .write_zcull_ptr = gr_gk20a_write_zcull_ptr, + .write_pm_ptr = gr_gk20a_write_pm_ptr, + .init_elcg_mode = gr_gk20a_init_elcg_mode, + .load_tpc_mask = gr_gm20b_load_tpc_mask, + .inval_icache = gr_gk20a_inval_icache, + .trigger_suspend = gr_gk20a_trigger_suspend, + .wait_for_pause = gr_gk20a_wait_for_pause, + .resume_from_pause = gr_gk20a_resume_from_pause, + .clear_sm_errors = gr_gk20a_clear_sm_errors, + .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, + .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, + .sm_debugger_attached = gk20a_gr_sm_debugger_attached, + .suspend_single_sm = gk20a_gr_suspend_single_sm, + .suspend_all_sms = gk20a_gr_suspend_all_sms, + .resume_single_sm = gk20a_gr_resume_single_sm, + .resume_all_sms = gk20a_gr_resume_all_sms, + .get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr, + .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr, + .get_sm_no_lock_down_hww_global_esr_mask = + gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, + .lock_down_sm = gk20a_gr_lock_down_sm, + .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, + .clear_sm_hww = gm20b_gr_clear_sm_hww, + .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, + .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, + .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data, + .set_boosted_ctx = NULL, + .update_boosted_ctx = NULL, + }, + .fb = { + .reset = fb_gk20a_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = fb_gm20b_init_fs_state, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gm20b_fb_compression_page_size, + .compressible_page_size = gm20b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .read_wpr_info = gm20b_fb_read_wpr_info, + .is_debug_mode_enabled = NULL, + .set_debug_mode = vgpu_mm_mmu_set_debug_mode, + .tlb_invalidate = vgpu_mm_tlb_invalidate, + }, + .clock_gating = { + .slcg_bus_load_gating_prod = + gm20b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gm20b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gm20b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gm20b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gm20b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gm20b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gm20b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gm20b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gm20b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gm20b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gm20b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gm20b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gm20b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gm20b_blcg_bus_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gm20b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gm20b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gm20b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gm20b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gm20b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gm20b_blcg_pwr_csb_load_gating_prod, + .blcg_xbar_load_gating_prod = + gm20b_blcg_xbar_load_gating_prod, + .blcg_pmu_load_gating_prod = + gm20b_blcg_pmu_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gm20b_pg_gr_load_gating_prod, + }, + .fifo = { + .init_fifo_setup_hw = vgpu_init_fifo_setup_hw, + .bind_channel = vgpu_channel_bind, + .unbind_channel = vgpu_channel_unbind, + .disable_channel = vgpu_channel_disable, + .enable_channel = vgpu_channel_enable, + .alloc_inst = vgpu_channel_alloc_inst, + .free_inst = vgpu_channel_free_inst, + .setup_ramfc = vgpu_channel_setup_ramfc, + .channel_set_priority = vgpu_channel_set_priority, + .channel_set_timeslice = vgpu_channel_set_timeslice, + .default_timeslice_us = vgpu_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gk20a_fifo_userd_gp_get, + .userd_gp_put = gk20a_fifo_userd_gp_put, + .userd_pb_get = gk20a_fifo_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = vgpu_fifo_preempt_channel, + .preempt_tsg = vgpu_fifo_preempt_tsg, + .enable_tsg = gk20a_enable_tsg, + .disable_tsg = gk20a_disable_tsg, + .tsg_verify_channel_status = NULL, + .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + .update_runlist = vgpu_fifo_update_runlist, + .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, + .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, + .wait_engine_idle = vgpu_fifo_wait_engine_idle, + .get_num_fifos = gm20b_fifo_get_num_fifos, + .get_pbdma_signature = gk20a_fifo_get_pbdma_signature, + .set_runlist_interleave = vgpu_fifo_set_runlist_interleave, + .tsg_set_timeslice = vgpu_tsg_set_timeslice, + .tsg_open = vgpu_tsg_open, + .force_reset_ch = vgpu_fifo_force_reset_ch, + .engine_enum_from_type = gk20a_fifo_engine_enum_from_type, + .device_info_data_parse = gm20b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = vgpu_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, + .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gk20a_dump_eng_status, + .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, + .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, + .is_preempt_pending = gk20a_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, + .handle_sched_error = gk20a_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, + .tsg_bind_channel = vgpu_tsg_bind_channel, + .tsg_unbind_channel = vgpu_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, +#endif + }, + .gr_ctx = { + .get_netlist_name = gr_gm20b_get_netlist_name, + .is_fw_defined = gr_gm20b_is_firmware_defined, + }, + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = vgpu_locked_gmmu_map, + .gmmu_unmap = vgpu_locked_gmmu_unmap, + .vm_bind_channel = vgpu_vm_bind_channel, + .fb_flush = vgpu_mm_fb_flush, + .l2_invalidate = vgpu_mm_l2_invalidate, + .l2_flush = vgpu_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gm20b_mm_get_default_big_page_size, + .gpu_phys_addr = gm20b_gpu_phys_addr, + .get_iommu_bit = gk20a_mm_get_iommu_bit, + .get_mmu_levels = gk20a_mm_get_mmu_levels, + .init_pdb = gk20a_mm_init_pdb, + .init_mm_setup_hw = NULL, + .is_bar1_supported = gm20b_mm_is_bar1_supported, + .init_inst_block = gk20a_init_inst_block, + .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, + }, + .therm = { + .init_therm_setup_hw = gm20b_init_therm_setup_hw, + .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, + }, + .pmu = { + .pmu_setup_elpg = gm20b_pmu_setup_elpg, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .write_dmatrfbase = gm20b_write_dmatrfbase, + .pmu_elpg_statistics = gk20a_pmu_elpg_statistics, + .pmu_pg_init_param = NULL, + .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .pmu_is_lpwr_feature_supported = NULL, + .pmu_lpwr_enable_pg = NULL, + .pmu_lpwr_disable_pg = NULL, + .pmu_pg_param_post_init = NULL, + .dump_secure_fuses = pmu_dump_security_fuses_gm20b, + .reset_engine = gk20a_pmu_engine_reset, + .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, + }, + .clk = { + .init_clk_support = gm20b_init_clk_support, + .suspend_clk_support = gm20b_suspend_clk_support, +#ifdef CONFIG_DEBUG_FS + .init_debugfs = gm20b_clk_init_debugfs, +#endif + .get_voltage = gm20b_clk_get_voltage, + .get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter, + .pll_reg_write = gm20b_clk_pll_reg_write, + .get_pll_debug_data = gm20b_clk_get_pll_debug_data, + }, + .regops = { + .get_global_whitelist_ranges = + gm20b_get_global_whitelist_ranges, + .get_global_whitelist_ranges_count = + gm20b_get_global_whitelist_ranges_count, + .get_context_whitelist_ranges = + gm20b_get_context_whitelist_ranges, + .get_context_whitelist_ranges_count = + gm20b_get_context_whitelist_ranges_count, + .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist, + .get_runcontrol_whitelist_count = + gm20b_get_runcontrol_whitelist_count, + .get_runcontrol_whitelist_ranges = + gm20b_get_runcontrol_whitelist_ranges, + .get_runcontrol_whitelist_ranges_count = + gm20b_get_runcontrol_whitelist_ranges_count, + .get_qctl_whitelist = gm20b_get_qctl_whitelist, + .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, + .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges, + .get_qctl_whitelist_ranges_count = + gm20b_get_qctl_whitelist_ranges_count, + .apply_smpc_war = gm20b_apply_smpc_war, + }, + .mc = { + .intr_enable = mc_gk20a_intr_enable, + .intr_unit_config = mc_gk20a_intr_unit_config, + .isr_stall = mc_gk20a_isr_stall, + .intr_stall = mc_gk20a_intr_stall, + .intr_stall_pause = mc_gk20a_intr_stall_pause, + .intr_stall_resume = mc_gk20a_intr_stall_resume, + .intr_nonstall = mc_gk20a_intr_nonstall, + .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause, + .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gk20a_is_intr1_pending, + }, + .debug = { + .show_dump = NULL, + }, + .dbg_session_ops = { + .exec_reg_ops = vgpu_exec_regops, + .dbg_set_powergate = vgpu_dbg_set_powergate, + .check_and_set_global_reservation = + vgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + vgpu_check_and_set_context_reservation, + .release_profiler_reservation = + vgpu_release_profiler_reservation, + .perfbuffer_enable = vgpu_perfbuffer_enable, + .perfbuffer_disable = vgpu_perfbuffer_disable, + }, + .cde = { + .get_program_numbers = gm20b_cde_get_program_numbers, + }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = vgpu_read_ptimer, + .get_timestamps_zipper = vgpu_get_timestamps_zipper, + .bar1_bind = gm20b_bus_bar1_bind, + }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = vgpu_css_enable_snapshot_buffer, + .disable_snapshot = vgpu_css_release_snapshot_buffer, + .check_data_available = vgpu_css_flush_snapshots, + .detach_snapshot = vgpu_css_detach, + .set_handled_snapshots = NULL, + .allocate_perfmon_ids = NULL, + .release_perfmon_ids = NULL, + }, +#endif + .falcon = { + .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, + }, + .priv_ring = { + .isr = gk20a_priv_ring_isr, + }, + .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, + .get_litter_value = gm20b_get_litter_value, +}; + int vgpu_gm20b_init_hal(struct gk20a *g) { - int err; + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + u32 val; - err = gm20b_init_hal(g); - if (err) - return err; - vgpu_init_hal_common(g); - vgpu_gm20b_init_gr_ops(&g->ops); + gops->ltc = vgpu_gm20b_ops.ltc; + gops->ce2 = vgpu_gm20b_ops.ce2; + gops->gr = vgpu_gm20b_ops.gr; + gops->fb = vgpu_gm20b_ops.fb; + gops->clock_gating = vgpu_gm20b_ops.clock_gating; + gops->fifo = vgpu_gm20b_ops.fifo; + gops->gr_ctx = vgpu_gm20b_ops.gr_ctx; + gops->mm = vgpu_gm20b_ops.mm; + gops->therm = vgpu_gm20b_ops.therm; + gops->pmu = vgpu_gm20b_ops.pmu; + /* + * clk must be assigned member by member + * since some clk ops are assigned during probe prior to HAL init + */ + gops->clk.init_clk_support = vgpu_gm20b_ops.clk.init_clk_support; + gops->clk.suspend_clk_support = vgpu_gm20b_ops.clk.suspend_clk_support; + gops->clk.get_voltage = vgpu_gm20b_ops.clk.get_voltage; + gops->clk.get_gpcclk_clock_counter = + vgpu_gm20b_ops.clk.get_gpcclk_clock_counter; + gops->clk.pll_reg_write = vgpu_gm20b_ops.clk.pll_reg_write; + gops->clk.get_pll_debug_data = vgpu_gm20b_ops.clk.get_pll_debug_data; + + gops->regops = vgpu_gm20b_ops.regops; + gops->mc = vgpu_gm20b_ops.mc; + gops->dbg_session_ops = vgpu_gm20b_ops.dbg_session_ops; + gops->debug = vgpu_gm20b_ops.debug; + gops->cde = vgpu_gm20b_ops.cde; + gops->bus = vgpu_gm20b_ops.bus; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = vgpu_gm20b_ops.css; +#endif + gops->falcon = vgpu_gm20b_ops.falcon; + + gops->priv_ring = vgpu_gm20b_ops.priv_ring; + + /* Lone functions */ + gops->chip_init_gpu_characteristics = + vgpu_gm20b_ops.chip_init_gpu_characteristics; + gops->get_litter_value = vgpu_gm20b_ops.get_litter_value; + + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); + +#ifdef CONFIG_TEGRA_ACR + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + } else { + val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); + if (!val) { + gk20a_dbg_info("priv security is disabled in HW"); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + } else { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + } + } +#else + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + gk20a_dbg_info("running ASIM with PRIV security disabled"); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + } else { + val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); + if (!val) { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + } else { + gk20a_dbg_info("priv security is not supported but enabled"); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + return -EPERM; + } + } +#endif + + /* priv security dependent ops */ + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + /* Add in ops from gm20b acr */ + gops->pmu.is_pmu_supported = gm20b_is_pmu_supported; + gops->pmu.prepare_ucode = prepare_ucode_blob; + gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn; + gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap; + gops->pmu.is_priv_load = gm20b_is_priv_load; + gops->pmu.get_wpr = gm20b_wpr_info; + gops->pmu.alloc_blob_space = gm20b_alloc_blob_space; + gops->pmu.pmu_populate_loader_cfg = + gm20b_pmu_populate_loader_cfg; + gops->pmu.flcn_populate_bl_dmem_desc = + gm20b_flcn_populate_bl_dmem_desc; + gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt; + gops->pmu.falcon_clear_halt_interrupt_status = + clear_halt_interrupt_status; + gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1; + + gops->pmu.init_wpr_region = gm20b_pmu_init_acr; + gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; + + gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; + } else { + /* Inherit from gk20a */ + gops->pmu.is_pmu_supported = gk20a_is_pmu_supported; + gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob; + gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; + gops->pmu.pmu_nsbootstrap = pmu_bootstrap; + + gops->pmu.load_lsfalcon_ucode = NULL; + gops->pmu.init_wpr_region = NULL; + + gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; + } + + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); + g->pmu_lsf_pmu_wpr_init_done = 0; + g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; + + gm20b_init_uncompressed_kind_map(); + gm20b_init_kind_attr(); + + g->name = "gm20b"; + + c->twod_class = FERMI_TWOD_A; + c->threed_class = MAXWELL_B; + c->compute_class = MAXWELL_COMPUTE_B; + c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = MAXWELL_DMA_COPY_A; return 0; } diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index ec2fcd8e1..fa6109ad8 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -31,7 +31,7 @@ #include -static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, +void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx) { struct tegra_vgpu_cmd_msg msg = {0}; @@ -59,7 +59,7 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, nvgpu_kfree(g, gr_ctx); } -static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, +int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, struct gr_ctx_desc **__gr_ctx, struct vm_gk20a *vm, u32 class, @@ -115,7 +115,7 @@ fail: return err; } -static int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, +int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, struct gr_ctx_desc *gr_ctx, struct vm_gk20a *vm, u32 class, u32 graphics_preempt_mode, @@ -267,7 +267,7 @@ fail: return err; } -static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, +int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, u32 graphics_preempt_mode, u32 compute_preempt_mode) { @@ -316,7 +316,7 @@ static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, return err; } -static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) +int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); int err; @@ -334,14 +334,3 @@ static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) return 0; } - -void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops) -{ - vgpu_gm20b_init_gr_ops(gops); - gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx; - gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx; - gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state; - gops->gr.set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode; - gops->gr.set_ctxsw_preemption_mode = - vgpu_gr_gp10b_set_ctxsw_preemption_mode; -} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h index 9505749ea..baf5a8e9b 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,21 @@ #include "gk20a/gk20a.h" -void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops); +void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx); +int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, + struct gr_ctx_desc **__gr_ctx, + struct vm_gk20a *vm, + u32 class, + u32 flags); +int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, + struct gr_ctx_desc *gr_ctx, + struct vm_gk20a *vm, u32 class, + u32 graphics_preempt_mode, + u32 compute_preempt_mode); +int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, + u32 graphics_preempt_mode, + u32 compute_preempt_mode); +int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 8a367f940..aae74e3fa 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -21,24 +21,626 @@ */ #include "vgpu/vgpu.h" +#include "vgpu/fifo_vgpu.h" +#include "vgpu/gr_vgpu.h" +#include "vgpu/ltc_vgpu.h" +#include "vgpu/mm_vgpu.h" +#include "vgpu/dbg_vgpu.h" +#include "vgpu/fecs_trace_vgpu.h" +#include "vgpu/css_vgpu.h" +#include "gp10b/gp10b.h" #include "gp10b/hal_gp10b.h" +#include "vgpu/gm20b/vgpu_gr_gm20b.h" #include "vgpu_gr_gp10b.h" -#include "vgpu_fifo_gp10b.h" #include "vgpu_mm_gp10b.h" +#include "gk20a/bus_gk20a.h" +#include "gk20a/pramin_gk20a.h" +#include "gk20a/flcn_gk20a.h" +#include "gk20a/mc_gk20a.h" +#include "gk20a/fb_gk20a.h" + +#include "gp10b/mc_gp10b.h" +#include "gp10b/ltc_gp10b.h" +#include "gp10b/mm_gp10b.h" +#include "gp10b/ce_gp10b.h" +#include "gp10b/fb_gp10b.h" +#include "gp10b/pmu_gp10b.h" +#include "gp10b/gr_ctx_gp10b.h" +#include "gp10b/fifo_gp10b.h" +#include "gp10b/gp10b_gating_reglist.h" +#include "gp10b/regops_gp10b.h" +#include "gp10b/cde_gp10b.h" +#include "gp10b/therm_gp10b.h" +#include "gp10b/priv_ring_gp10b.h" + +#include "gm20b/ltc_gm20b.h" +#include "gm20b/gr_gm20b.h" +#include "gm20b/fifo_gm20b.h" +#include "gm20b/acr_gm20b.h" +#include "gm20b/pmu_gm20b.h" +#include "gm20b/fb_gm20b.h" +#include "gm20b/mm_gm20b.h" + +#include + +#include +#include +#include +#include +#include +#include + +static const struct gpu_ops vgpu_gp10b_ops = { + .ltc = { + .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = gm20b_ltc_init_cbc, + .init_fs_state = vgpu_ltc_init_fs_state, + .init_comptags = vgpu_ltc_init_comptags, + .cbc_ctrl = NULL, + .isr = gp10b_ltc_isr, + .cbc_fix_config = gm20b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, + .set_enabled = gp10b_ltc_set_enabled, + }, + .ce2 = { + .isr_stall = gp10b_ce_isr, + .isr_nonstall = gp10b_ce_nonstall_isr, + .get_num_pce = vgpu_ce_get_num_pce, + }, + .gr = { + .init_gpc_mmu = gr_gm20b_init_gpc_mmu, + .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, + .cb_size_default = gr_gp10b_cb_size_default, + .calc_global_ctx_buffer_size = + gr_gp10b_calc_global_ctx_buffer_size, + .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb, + .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, + .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, + .commit_global_pagepool = gr_gp10b_commit_global_pagepool, + .handle_sw_method = gr_gp10b_handle_sw_method, + .set_alpha_circular_buffer_size = + gr_gp10b_set_alpha_circular_buffer_size, + .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size, + .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions, + .is_valid_class = gr_gp10b_is_valid_class, + .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, + .is_valid_compute_class = gr_gp10b_is_valid_compute_class, + .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, + .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, + .init_fs_state = vgpu_gm20b_init_fs_state, + .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, + .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, + .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, + .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, + .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, + .free_channel_ctx = vgpu_gr_free_channel_ctx, + .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, + .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, + .get_zcull_info = vgpu_gr_get_zcull_info, + .is_tpc_addr = gr_gm20b_is_tpc_addr, + .get_tpc_num = gr_gm20b_get_tpc_num, + .detect_sm_arch = vgpu_gr_detect_sm_arch, + .add_zbc_color = gr_gp10b_add_zbc_color, + .add_zbc_depth = gr_gp10b_add_zbc_depth, + .zbc_set_table = vgpu_gr_add_zbc, + .zbc_query_table = vgpu_gr_query_zbc, + .pmu_save_zbc = gk20a_pmu_save_zbc, + .add_zbc = gr_gk20a_add_zbc, + .pagepool_default_size = gr_gp10b_pagepool_default_size, + .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, + .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, + .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx, + .update_ctxsw_preemption_mode = + gr_gp10b_update_ctxsw_preemption_mode, + .dump_gr_regs = NULL, + .update_pc_sampling = gr_gm20b_update_pc_sampling, + .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, + .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, + .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, + .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, + .get_max_fbps_count = vgpu_gr_get_max_fbps_count, + .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, + .wait_empty = gr_gp10b_wait_empty, + .init_cyclestats = gr_gp10b_init_cyclestats, + .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, + .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, + .bpt_reg_info = gr_gm20b_bpt_reg_info, + .get_access_map = gr_gp10b_get_access_map, + .handle_fecs_error = gr_gp10b_handle_fecs_error, + .handle_sm_exception = gr_gp10b_handle_sm_exception, + .handle_tex_exception = gr_gp10b_handle_tex_exception, + .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions, + .enable_exceptions = gk20a_gr_enable_exceptions, + .get_lrf_tex_ltc_dram_override = get_ecc_override_val, + .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, + .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, + .record_sm_error_state = gm20b_gr_record_sm_error_state, + .update_sm_error_state = gm20b_gr_update_sm_error_state, + .clear_sm_error_state = vgpu_gr_clear_sm_error_state, + .suspend_contexts = vgpu_gr_suspend_contexts, + .resume_contexts = vgpu_gr_resume_contexts, + .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, + .fuse_override = gp10b_gr_fuse_override, + .init_sm_id_table = gr_gk20a_init_sm_id_table, + .load_smid_config = gr_gp10b_load_smid_config, + .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, + .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, + .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, + .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, + .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, + .setup_rop_mapping = gr_gk20a_setup_rop_mapping, + .program_zcull_mapping = gr_gk20a_program_zcull_mapping, + .commit_global_timeslice = gr_gk20a_commit_global_timeslice, + .commit_inst = vgpu_gr_commit_inst, + .write_zcull_ptr = gr_gk20a_write_zcull_ptr, + .write_pm_ptr = gr_gk20a_write_pm_ptr, + .init_elcg_mode = gr_gk20a_init_elcg_mode, + .load_tpc_mask = gr_gm20b_load_tpc_mask, + .inval_icache = gr_gk20a_inval_icache, + .trigger_suspend = gr_gk20a_trigger_suspend, + .wait_for_pause = gr_gk20a_wait_for_pause, + .resume_from_pause = gr_gk20a_resume_from_pause, + .clear_sm_errors = gr_gk20a_clear_sm_errors, + .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, + .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, + .sm_debugger_attached = gk20a_gr_sm_debugger_attached, + .suspend_single_sm = gk20a_gr_suspend_single_sm, + .suspend_all_sms = gk20a_gr_suspend_all_sms, + .resume_single_sm = gk20a_gr_resume_single_sm, + .resume_all_sms = gk20a_gr_resume_all_sms, + .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr, + .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr, + .get_sm_no_lock_down_hww_global_esr_mask = + gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, + .lock_down_sm = gk20a_gr_lock_down_sm, + .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, + .clear_sm_hww = gm20b_gr_clear_sm_hww, + .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, + .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, + .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .set_boosted_ctx = NULL, + .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, + .set_czf_bypass = gr_gp10b_set_czf_bypass, + .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception, + .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va, + .init_preemption_state = gr_gp10b_init_preemption_state, + .update_boosted_ctx = NULL, + .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, + .create_gr_sysfs = gr_gp10b_create_sysfs, + .set_ctxsw_preemption_mode = + vgpu_gr_gp10b_set_ctxsw_preemption_mode, + .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, + }, + .fb = { + .reset = fb_gk20a_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = fb_gm20b_init_fs_state, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gp10b_fb_compression_page_size, + .compressible_page_size = gp10b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .read_wpr_info = gm20b_fb_read_wpr_info, + .is_debug_mode_enabled = NULL, + .set_debug_mode = vgpu_mm_mmu_set_debug_mode, + .tlb_invalidate = vgpu_mm_tlb_invalidate, + }, + .clock_gating = { + .slcg_bus_load_gating_prod = + gp10b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gp10b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gp10b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gp10b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gp10b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gp10b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gp10b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gp10b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gp10b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gp10b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gp10b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gp10b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gp10b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gp10b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gp10b_blcg_ce_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gp10b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gp10b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gp10b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gp10b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gp10b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gp10b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gp10b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gp10b_blcg_xbar_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gp10b_pg_gr_load_gating_prod, + }, + .fifo = { + .init_fifo_setup_hw = vgpu_init_fifo_setup_hw, + .bind_channel = vgpu_channel_bind, + .unbind_channel = vgpu_channel_unbind, + .disable_channel = vgpu_channel_disable, + .enable_channel = vgpu_channel_enable, + .alloc_inst = vgpu_channel_alloc_inst, + .free_inst = vgpu_channel_free_inst, + .setup_ramfc = vgpu_channel_setup_ramfc, + .channel_set_priority = vgpu_channel_set_priority, + .channel_set_timeslice = vgpu_channel_set_timeslice, + .default_timeslice_us = vgpu_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gk20a_fifo_userd_gp_get, + .userd_gp_put = gk20a_fifo_userd_gp_put, + .userd_pb_get = gk20a_fifo_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = vgpu_fifo_preempt_channel, + .preempt_tsg = vgpu_fifo_preempt_tsg, + .enable_tsg = gk20a_enable_tsg, + .disable_tsg = gk20a_disable_tsg, + .tsg_verify_channel_status = NULL, + .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + .reschedule_runlist = NULL, + .update_runlist = vgpu_fifo_update_runlist, + .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, + .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, + .wait_engine_idle = vgpu_fifo_wait_engine_idle, + .get_num_fifos = gm20b_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = vgpu_fifo_set_runlist_interleave, + .tsg_set_timeslice = vgpu_tsg_set_timeslice, + .tsg_open = vgpu_tsg_open, + .force_reset_ch = vgpu_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = vgpu_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, + .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gk20a_dump_eng_status, + .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, + .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, + .is_preempt_pending = gk20a_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, + .handle_sched_error = gk20a_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, + .tsg_bind_channel = vgpu_tsg_bind_channel, + .tsg_unbind_channel = vgpu_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = NULL, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + }, + .gr_ctx = { + .get_netlist_name = gr_gp10b_get_netlist_name, + .is_fw_defined = gr_gp10b_is_firmware_defined, + }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = vgpu_alloc_user_buffer, + .free_user_buffer = vgpu_free_user_buffer, + .mmap_user_buffer = vgpu_mmap_user_buffer, + .init = vgpu_fecs_trace_init, + .deinit = vgpu_fecs_trace_deinit, + .enable = vgpu_fecs_trace_enable, + .disable = vgpu_fecs_trace_disable, + .is_enabled = vgpu_fecs_trace_is_enabled, + .reset = NULL, + .flush = NULL, + .poll = vgpu_fecs_trace_poll, + .bind_channel = NULL, + .unbind_channel = NULL, + .max_entries = vgpu_fecs_trace_max_entries, + .set_filter = vgpu_fecs_trace_set_filter, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + /* FIXME: add support for sparse mappings */ + .support_sparse = NULL, + .gmmu_map = vgpu_gp10b_locked_gmmu_map, + .gmmu_unmap = vgpu_locked_gmmu_unmap, + .vm_bind_channel = vgpu_vm_bind_channel, + .fb_flush = vgpu_mm_fb_flush, + .l2_invalidate = vgpu_mm_l2_invalidate, + .l2_flush = vgpu_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gm20b_gpu_phys_addr, + .get_iommu_bit = gk20a_mm_get_iommu_bit, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, + .is_bar1_supported = gm20b_mm_is_bar1_supported, + .init_inst_block = gk20a_init_inst_block, + .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gp10b_remove_bar2_vm, + }, + .pramin = { + .enter = gk20a_pramin_enter, + .exit = gk20a_pramin_exit, + .data032_r = pram_data032_r, + }, + .therm = { + .init_therm_setup_hw = gp10b_init_therm_setup_hw, + .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, + }, + .pmu = { + .pmu_setup_elpg = gp10b_pmu_setup_elpg, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_elpg_statistics = gp10b_pmu_elpg_statistics, + .pmu_pg_init_param = gp10b_pg_gr_init, + .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .dump_secure_fuses = pmu_dump_security_fuses_gp10b, + .reset_engine = gk20a_pmu_engine_reset, + .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, + }, + .regops = { + .get_global_whitelist_ranges = + gp10b_get_global_whitelist_ranges, + .get_global_whitelist_ranges_count = + gp10b_get_global_whitelist_ranges_count, + .get_context_whitelist_ranges = + gp10b_get_context_whitelist_ranges, + .get_context_whitelist_ranges_count = + gp10b_get_context_whitelist_ranges_count, + .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, + .get_runcontrol_whitelist_count = + gp10b_get_runcontrol_whitelist_count, + .get_runcontrol_whitelist_ranges = + gp10b_get_runcontrol_whitelist_ranges, + .get_runcontrol_whitelist_ranges_count = + gp10b_get_runcontrol_whitelist_ranges_count, + .get_qctl_whitelist = gp10b_get_qctl_whitelist, + .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, + .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges, + .get_qctl_whitelist_ranges_count = + gp10b_get_qctl_whitelist_ranges_count, + .apply_smpc_war = gp10b_apply_smpc_war, + }, + .mc = { + .intr_enable = mc_gp10b_intr_enable, + .intr_unit_config = mc_gp10b_intr_unit_config, + .isr_stall = mc_gp10b_isr_stall, + .intr_stall = mc_gp10b_intr_stall, + .intr_stall_pause = mc_gp10b_intr_stall_pause, + .intr_stall_resume = mc_gp10b_intr_stall_resume, + .intr_nonstall = mc_gp10b_intr_nonstall, + .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, + .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gp10b_is_intr1_pending, + }, + .debug = { + .show_dump = NULL, + }, + .dbg_session_ops = { + .exec_reg_ops = vgpu_exec_regops, + .dbg_set_powergate = vgpu_dbg_set_powergate, + .check_and_set_global_reservation = + vgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + vgpu_check_and_set_context_reservation, + .release_profiler_reservation = + vgpu_release_profiler_reservation, + .perfbuffer_enable = vgpu_perfbuffer_enable, + .perfbuffer_disable = vgpu_perfbuffer_disable, + }, + .cde = { + .get_program_numbers = gp10b_cde_get_program_numbers, + .need_scatter_buffer = gp10b_need_scatter_buffer, + .populate_scatter_buffer = gp10b_populate_scatter_buffer, + }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = vgpu_read_ptimer, + .get_timestamps_zipper = vgpu_get_timestamps_zipper, + .bar1_bind = gk20a_bus_bar1_bind, + }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = vgpu_css_enable_snapshot_buffer, + .disable_snapshot = vgpu_css_release_snapshot_buffer, + .check_data_available = vgpu_css_flush_snapshots, + .detach_snapshot = vgpu_css_detach, + .set_handled_snapshots = NULL, + .allocate_perfmon_ids = NULL, + .release_perfmon_ids = NULL, + }, +#endif + .falcon = { + .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, + }, + .priv_ring = { + .isr = gp10b_priv_ring_isr, + }, + .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, + .get_litter_value = gp10b_get_litter_value, +}; + int vgpu_gp10b_init_hal(struct gk20a *g) { - int err; + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + u32 val; - gk20a_dbg_fn(""); + gops->ltc = vgpu_gp10b_ops.ltc; + gops->ce2 = vgpu_gp10b_ops.ce2; + gops->gr = vgpu_gp10b_ops.gr; + gops->fb = vgpu_gp10b_ops.fb; + gops->clock_gating = vgpu_gp10b_ops.clock_gating; + gops->fifo = vgpu_gp10b_ops.fifo; + gops->gr_ctx = vgpu_gp10b_ops.gr_ctx; + gops->fecs_trace = vgpu_gp10b_ops.fecs_trace; + gops->mm = vgpu_gp10b_ops.mm; + gops->pramin = vgpu_gp10b_ops.pramin; + gops->therm = vgpu_gp10b_ops.therm; + gops->pmu = vgpu_gp10b_ops.pmu; + gops->regops = vgpu_gp10b_ops.regops; + gops->mc = vgpu_gp10b_ops.mc; + gops->debug = vgpu_gp10b_ops.debug; + gops->dbg_session_ops = vgpu_gp10b_ops.dbg_session_ops; + gops->cde = vgpu_gp10b_ops.cde; + gops->bus = vgpu_gp10b_ops.bus; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = vgpu_gp10b_ops.css; +#endif + gops->falcon = vgpu_gp10b_ops.falcon; - err = gp10b_init_hal(g); - if (err) - return err; + gops->priv_ring = vgpu_gp10b_ops.priv_ring; + + /* Lone Functions */ + gops->chip_init_gpu_characteristics = + vgpu_gp10b_ops.chip_init_gpu_characteristics; + gops->get_litter_value = vgpu_gp10b_ops.get_litter_value; + + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); + __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); + +#ifdef CONFIG_TEGRA_ACR + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + } else if (g->is_virtual) { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + } else { + val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); + if (val) { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + } else { + gk20a_dbg_info("priv security is disabled in HW"); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + } + } +#else + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + gk20a_dbg_info("running simulator with PRIV security disabled"); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + } else { + val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); + if (val) { + gk20a_dbg_info("priv security is not supported but enabled"); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + return -EPERM; + } else { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + } + } +#endif + + /* priv security dependent ops */ + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + /* Add in ops from gm20b acr */ + gops->pmu.is_pmu_supported = gm20b_is_pmu_supported, + gops->pmu.prepare_ucode = prepare_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, + gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, + gops->pmu.is_priv_load = gm20b_is_priv_load, + gops->pmu.get_wpr = gm20b_wpr_info, + gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, + gops->pmu.pmu_populate_loader_cfg = + gm20b_pmu_populate_loader_cfg, + gops->pmu.flcn_populate_bl_dmem_desc = + gm20b_flcn_populate_bl_dmem_desc, + gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, + gops->pmu.falcon_clear_halt_interrupt_status = + clear_halt_interrupt_status, + gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, + + gops->pmu.init_wpr_region = gm20b_pmu_init_acr; + gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; + gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; + gops->pmu.is_priv_load = gp10b_is_priv_load; + + gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; + } else { + /* Inherit from gk20a */ + gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, + gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, + gops->pmu.pmu_nsbootstrap = pmu_bootstrap, + + gops->pmu.load_lsfalcon_ucode = NULL; + gops->pmu.init_wpr_region = NULL; + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; + + gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; + } + + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); + g->pmu_lsf_pmu_wpr_init_done = 0; + g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; + + gp10b_init_uncompressed_kind_map(); + gp10b_init_kind_attr(); + + g->name = "gp10b"; + + c->twod_class = FERMI_TWOD_A; + c->threed_class = PASCAL_A; + c->compute_class = PASCAL_COMPUTE_A; + c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = PASCAL_DMA_COPY_A; - vgpu_init_hal_common(g); - vgpu_gp10b_init_gr_ops(&g->ops); - vgpu_gp10b_init_fifo_ops(&g->ops); - vgpu_gp10b_init_mm_ops(&g->ops); return 0; } diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c index cb7008ba1..f063961f7 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c @@ -28,7 +28,7 @@ #include -static int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) +int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) { g->mm.bypass_smmu = true; g->mm.disable_bigpage = true; @@ -47,7 +47,7 @@ static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, return 0; } -static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, +u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, u64 map_offset, struct nvgpu_sgt *sgt, u64 buffer_offset, @@ -200,14 +200,3 @@ fail: return 0; } - -void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops) -{ - gk20a_dbg_fn(""); - - gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map; - gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw; - - /* FIXME: add support for sparse mappings */ - gops->mm.support_sparse = NULL; -} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h index a8f0b7bc7..fd6760ff8 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,21 @@ #include "gk20a/gk20a.h" -void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops); +u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, + u64 map_offset, + struct nvgpu_sgt *sgt, + u64 buffer_offset, + u64 size, + int pgsz_idx, + u8 kind_v, + u32 ctag_offset, + u32 flags, + int rw_flag, + bool clear_ctags, + bool sparse, + bool priv, + struct vm_gk20a_mapping_batch *batch, + enum nvgpu_aperture aperture); +int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 7f267f26e..96d21c0a7 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c @@ -26,11 +26,12 @@ #include #include "vgpu/vgpu.h" +#include "vgpu/gr_vgpu.h" #include "gk20a/dbg_gpu_gk20a.h" #include -static void vgpu_gr_detect_sm_arch(struct gk20a *g) +void vgpu_gr_detect_sm_arch(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); @@ -427,7 +428,7 @@ static void vgpu_gr_free_channel_pm_ctx(struct channel_gk20a *c) pm_ctx->mem.gpu_va = 0; } -static void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg) +void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg) { gk20a_dbg_fn(""); @@ -484,7 +485,7 @@ static int vgpu_gr_tsg_bind_gr_ctx(struct tsg_gk20a *tsg) return err; } -static int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, +int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, struct nvgpu_alloc_obj_ctx_args *args) { struct gk20a *g = c->g; @@ -666,7 +667,7 @@ cleanup: return -ENOMEM; } -static int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, +int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, struct channel_gk20a *c, u64 zcull_va, u32 mode) { @@ -686,7 +687,7 @@ static int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, return (err || msg.ret) ? -ENOMEM : 0; } -static int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, +int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, struct gr_zcull_info *zcull_params) { struct tegra_vgpu_cmd_msg msg; @@ -717,14 +718,14 @@ static int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, return 0; } -static u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) +u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); return priv->constants.gpc_tpc_mask[gpc_index]; } -static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) +u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); @@ -733,7 +734,7 @@ static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) return priv->constants.num_fbps; } -static u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g) +u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); @@ -742,7 +743,7 @@ static u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g) return priv->constants.fbp_en_mask; } -static u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g) +u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); @@ -751,7 +752,7 @@ static u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g) return priv->constants.ltc_per_fbp; } -static u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g) +u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); @@ -760,13 +761,13 @@ static u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g) return priv->constants.max_lts_per_ltc; } -static u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g) +u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g) { /* no one use it yet */ return NULL; } -static int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, +int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *zbc_val) { struct tegra_vgpu_cmd_msg msg = {0}; @@ -797,7 +798,7 @@ static int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, return (err || msg.ret) ? -ENOMEM : 0; } -static int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr, +int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr, struct zbc_query_params *query_params) { struct tegra_vgpu_cmd_msg msg = {0}; @@ -997,7 +998,7 @@ int vgpu_gr_nonstall_isr(struct gk20a *g, return 0; } -static int vgpu_gr_set_sm_debug_mode(struct gk20a *g, +int vgpu_gr_set_sm_debug_mode(struct gk20a *g, struct channel_gk20a *ch, u64 sms, bool enable) { struct tegra_vgpu_cmd_msg msg; @@ -1017,7 +1018,7 @@ static int vgpu_gr_set_sm_debug_mode(struct gk20a *g, return err ? err : msg.ret; } -static int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, +int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, struct channel_gk20a *ch, bool enable) { struct tegra_vgpu_cmd_msg msg; @@ -1041,7 +1042,7 @@ static int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, return err ? err : msg.ret; } -static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, +int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, struct channel_gk20a *ch, bool enable) { struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; @@ -1079,7 +1080,7 @@ static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, return err ? err : msg.ret; } -static int vgpu_gr_clear_sm_error_state(struct gk20a *g, +int vgpu_gr_clear_sm_error_state(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id) { struct gr_gk20a *gr = &g->gr; @@ -1172,7 +1173,7 @@ done: return err; } -static int vgpu_gr_suspend_contexts(struct gk20a *g, +int vgpu_gr_suspend_contexts(struct gk20a *g, struct dbg_session_gk20a *dbg_s, int *ctx_resident_ch_fd) { @@ -1180,7 +1181,7 @@ static int vgpu_gr_suspend_contexts(struct gk20a *g, ctx_resident_ch_fd, TEGRA_VGPU_CMD_SUSPEND_CONTEXTS); } -static int vgpu_gr_resume_contexts(struct gk20a *g, +int vgpu_gr_resume_contexts(struct gk20a *g, struct dbg_session_gk20a *dbg_s, int *ctx_resident_ch_fd) { @@ -1213,33 +1214,3 @@ void vgpu_gr_handle_sm_esr_event(struct gk20a *g, nvgpu_mutex_release(&g->dbg_sessions_lock); } - -void vgpu_init_gr_ops(struct gpu_ops *gops) -{ - gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch; - gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx; - gops->gr.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx; - gops->gr.alloc_gr_ctx = vgpu_gr_alloc_gr_ctx; - gops->gr.free_gr_ctx = vgpu_gr_free_gr_ctx; - gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull; - gops->gr.get_zcull_info = vgpu_gr_get_zcull_info; - gops->gr.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask; - gops->gr.get_max_fbps_count = vgpu_gr_get_max_fbps_count; - gops->gr.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask; - gops->gr.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp; - gops->gr.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc; - gops->gr.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask; - gops->gr.zbc_set_table = vgpu_gr_add_zbc; - gops->gr.zbc_query_table = vgpu_gr_query_zbc; - gops->gr.init_ctx_state = vgpu_gr_init_ctx_state; - gops->gr.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode; - gops->gr.update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode; - gops->gr.update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode; - gops->gr.clear_sm_error_state = vgpu_gr_clear_sm_error_state; - gops->gr.suspend_contexts = vgpu_gr_suspend_contexts; - gops->gr.resume_contexts = vgpu_gr_resume_contexts; - gops->gr.commit_inst = vgpu_gr_commit_inst; - gops->gr.dump_gr_regs = NULL; - gops->gr.set_boosted_ctx = NULL; - gops->gr.update_boosted_ctx = NULL; -} diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h index b6df991ee..5a5e09281 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h @@ -23,6 +23,50 @@ #ifndef _GR_VGPU_H_ #define _GR_VGPU_H_ +#include + +struct gk20a; +struct channel_gk20a; +struct nvgpu_alloc_obj_ctx_args; +struct gr_gk20a; +struct gr_zcull_info; +struct zbc_entry; +struct zbc_query_params; +struct dbg_session_gk20a; + +void vgpu_gr_detect_sm_arch(struct gk20a *g); +void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); +int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, + struct nvgpu_alloc_obj_ctx_args *args); +int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, + struct channel_gk20a *c, u64 zcull_va, + u32 mode); +int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, + struct gr_zcull_info *zcull_params); +u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); +u32 vgpu_gr_get_max_fbps_count(struct gk20a *g); +u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g); +u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g); +u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g); +u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g); +int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *zbc_val); +int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_query_params *query_params); +int vgpu_gr_set_sm_debug_mode(struct gk20a *g, + struct channel_gk20a *ch, u64 sms, bool enable); +int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, + struct channel_gk20a *ch, bool enable); +int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, + struct channel_gk20a *ch, bool enable); +int vgpu_gr_clear_sm_error_state(struct gk20a *g, + struct channel_gk20a *ch, u32 sm_id); +int vgpu_gr_suspend_contexts(struct gk20a *g, + struct dbg_session_gk20a *dbg_s, + int *ctx_resident_ch_fd); +int vgpu_gr_resume_contexts(struct gk20a *g, + struct dbg_session_gk20a *dbg_s, + int *ctx_resident_ch_fd); int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); #endif diff --git a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c index db39b3096..a68488724 100644 --- a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c @@ -1,7 +1,7 @@ /* * Virtualized GPU L2 * - * Copyright (c) 2014-2016 NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017 NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,8 +23,9 @@ */ #include "vgpu/vgpu.h" +#include "vgpu/ltc_vgpu.h" -static int vgpu_determine_L2_size_bytes(struct gk20a *g) +int vgpu_determine_L2_size_bytes(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); @@ -33,7 +34,7 @@ static int vgpu_determine_L2_size_bytes(struct gk20a *g) return priv->constants.l2_size; } -static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) +int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); u32 max_comptag_lines = 0; @@ -56,7 +57,7 @@ static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) return 0; } -static void vgpu_ltc_init_fs_state(struct gk20a *g) +void vgpu_ltc_init_fs_state(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); @@ -64,11 +65,3 @@ static void vgpu_ltc_init_fs_state(struct gk20a *g) g->ltc_count = priv->constants.ltc_count; } - -void vgpu_init_ltc_ops(struct gpu_ops *gops) -{ - gops->ltc.determine_L2_size_bytes = vgpu_determine_L2_size_bytes; - gops->ltc.init_comptags = vgpu_ltc_init_comptags; - gops->ltc.init_fs_state = vgpu_ltc_init_fs_state; - gops->ltc.cbc_ctrl = NULL; -} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.h similarity index 78% rename from drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h rename to drivers/gpu/nvgpu/vgpu/ltc_vgpu.h index 8dd016aa2..3437b4cb6 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,11 +20,14 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef __VGPU_FIFO_GP10B_H__ -#define __VGPU_FIFO_GP10B_H__ +#ifndef _LTC_VGPU_H_ +#define _LTC_VGPU_H_ -#include "gk20a/gk20a.h" +struct gk20a; +struct gr_gk20a; -void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops); +int vgpu_determine_L2_size_bytes(struct gk20a *g); +int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr); +void vgpu_ltc_init_fs_state(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c index 49517b9a6..8dcca0a15 100644 --- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c @@ -35,6 +35,7 @@ #include #include "vgpu/vgpu.h" +#include "vgpu/mm_vgpu.h" #include "gk20a/mm_gk20a.h" #include "gm20b/mm_gm20b.h" @@ -85,7 +86,7 @@ int vgpu_init_mm_support(struct gk20a *g) return err; } -static u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, +u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, u64 map_offset, struct nvgpu_sgt *sgt, u64 buffer_offset, @@ -171,7 +172,7 @@ fail: return 0; } -static void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, +void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, u64 vaddr, u64 size, int pgsz_idx, @@ -274,7 +275,7 @@ u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size) return addr; } -static int vgpu_vm_bind_channel(struct gk20a_as_share *as_share, +int vgpu_vm_bind_channel(struct gk20a_as_share *as_share, struct channel_gk20a *ch) { struct vm_gk20a *vm = as_share->vm; @@ -315,7 +316,7 @@ static void vgpu_cache_maint(u64 handle, u8 op) WARN_ON(err || msg.ret); } -static int vgpu_mm_fb_flush(struct gk20a *g) +int vgpu_mm_fb_flush(struct gk20a *g) { gk20a_dbg_fn(""); @@ -324,7 +325,7 @@ static int vgpu_mm_fb_flush(struct gk20a *g) return 0; } -static void vgpu_mm_l2_invalidate(struct gk20a *g) +void vgpu_mm_l2_invalidate(struct gk20a *g) { gk20a_dbg_fn(""); @@ -332,7 +333,7 @@ static void vgpu_mm_l2_invalidate(struct gk20a *g) vgpu_cache_maint(vgpu_get_handle(g), TEGRA_VGPU_L2_MAINT_INV); } -static void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate) +void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate) { u8 op; @@ -346,14 +347,14 @@ static void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate) vgpu_cache_maint(vgpu_get_handle(g), op); } -static void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) +void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) { gk20a_dbg_fn(""); nvgpu_err(g, "call to RM server not supported"); } -static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) +void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_mmu_debug_mode *p = &msg.params.mmu_debug_mode; @@ -367,19 +368,3 @@ static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); } - -void vgpu_init_mm_ops(struct gpu_ops *gops) -{ - gops->fb.is_debug_mode_enabled = NULL; - gops->fb.set_debug_mode = vgpu_mm_mmu_set_debug_mode; - gops->mm.gmmu_map = vgpu_locked_gmmu_map; - gops->mm.gmmu_unmap = vgpu_locked_gmmu_unmap; - gops->mm.vm_bind_channel = vgpu_vm_bind_channel; - gops->mm.fb_flush = vgpu_mm_fb_flush; - gops->mm.l2_invalidate = vgpu_mm_l2_invalidate; - gops->mm.l2_flush = vgpu_mm_l2_flush; - gops->fb.tlb_invalidate = vgpu_mm_tlb_invalidate; - gops->mm.get_iommu_bit = gk20a_mm_get_iommu_bit; - gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr; - gops->mm.init_mm_setup_hw = NULL; -} diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.h b/drivers/gpu/nvgpu/vgpu/mm_vgpu.h new file mode 100644 index 000000000..ed66282c8 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _MM_VGPU_H_ +#define _MM_VGPU_H_ + +u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, + u64 map_offset, + struct nvgpu_sgt *sgt, + u64 buffer_offset, + u64 size, + int pgsz_idx, + u8 kind_v, + u32 ctag_offset, + u32 flags, + int rw_flag, + bool clear_ctags, + bool sparse, + bool priv, + struct vm_gk20a_mapping_batch *batch, + enum nvgpu_aperture aperture); +void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, + u64 vaddr, + u64 size, + int pgsz_idx, + bool va_allocated, + int rw_flag, + bool sparse, + struct vm_gk20a_mapping_batch *batch); +int vgpu_vm_bind_channel(struct gk20a_as_share *as_share, + struct channel_gk20a *ch); +int vgpu_mm_fb_flush(struct gk20a *g); +void vgpu_mm_l2_invalidate(struct gk20a *g); +void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate); +void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb); +void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable); +#endif diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c index 39d789830..2be102e32 100644 --- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c @@ -27,10 +27,11 @@ #include "gk20a/platform_gk20a.h" #include "gk20a/tsg_gk20a.h" #include "vgpu.h" +#include "fifo_vgpu.h" #include -static int vgpu_tsg_open(struct tsg_gk20a *tsg) +int vgpu_tsg_open(struct tsg_gk20a *tsg) { struct tegra_vgpu_cmd_msg msg = {}; struct tegra_vgpu_tsg_open_params *p = @@ -52,7 +53,7 @@ static int vgpu_tsg_open(struct tsg_gk20a *tsg) return err; } -static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, +int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, struct channel_gk20a *ch) { struct tegra_vgpu_cmd_msg msg = {}; @@ -82,7 +83,7 @@ static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, return err; } -static int vgpu_tsg_unbind_channel(struct channel_gk20a *ch) +int vgpu_tsg_unbind_channel(struct channel_gk20a *ch) { struct tegra_vgpu_cmd_msg msg = {}; struct tegra_vgpu_tsg_bind_unbind_channel_params *p = @@ -105,7 +106,7 @@ static int vgpu_tsg_unbind_channel(struct channel_gk20a *ch) return err; } -static int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) +int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) { struct tegra_vgpu_cmd_msg msg = {0}; struct tegra_vgpu_tsg_timeslice_params *p = @@ -126,11 +127,3 @@ static int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) return err; } - -void vgpu_init_tsg_ops(struct gpu_ops *gops) -{ - gops->fifo.tsg_bind_channel = vgpu_tsg_bind_channel; - gops->fifo.tsg_unbind_channel = vgpu_tsg_unbind_channel; - gops->fifo.tsg_set_timeslice = vgpu_tsg_set_timeslice; - gops->fifo.tsg_open = vgpu_tsg_open; -} diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index b63202c1e..7949ff24b 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c @@ -378,7 +378,7 @@ int vgpu_init_gpu_characteristics(struct gk20a *g) return 0; } -static int vgpu_read_ptimer(struct gk20a *g, u64 *value) +int vgpu_read_ptimer(struct gk20a *g, u64 *value) { struct tegra_vgpu_cmd_msg msg = {0}; struct tegra_vgpu_read_ptimer_params *p = &msg.params.read_ptimer; @@ -441,27 +441,6 @@ int vgpu_get_timestamps_zipper(struct gk20a *g, return err; } -void vgpu_init_hal_common(struct gk20a *g) -{ - struct gpu_ops *gops = &g->ops; - - vgpu_init_fifo_ops(gops); - vgpu_init_gr_ops(gops); - vgpu_init_ltc_ops(gops); - vgpu_init_mm_ops(gops); - vgpu_init_debug_ops(gops); - vgpu_init_dbg_session_ops(gops); - vgpu_init_fecs_trace_ops(gops); - vgpu_init_tsg_ops(gops); -#if defined(CONFIG_GK20A_CYCLE_STATS) - vgpu_init_css_ops(gops); -#endif - vgpu_init_ce2_ops(gops); - gops->chip_init_gpu_characteristics = vgpu_init_gpu_characteristics; - gops->bus.read_ptimer = vgpu_read_ptimer; - gops->bus.get_timestamps_zipper = vgpu_get_timestamps_zipper; -} - static int vgpu_init_hal(struct gk20a *g) { u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h index 7364a8d9f..d5c49c0f9 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/vgpu.h @@ -94,16 +94,7 @@ int vgpu_fifo_nonstall_isr(struct gk20a *g, struct tegra_vgpu_fifo_nonstall_intr_info *info); int vgpu_ce2_nonstall_isr(struct gk20a *g, struct tegra_vgpu_ce2_nonstall_intr_info *info); -void vgpu_init_fifo_ops(struct gpu_ops *gops); -void vgpu_init_gr_ops(struct gpu_ops *gops); -void vgpu_init_ltc_ops(struct gpu_ops *gops); -void vgpu_init_mm_ops(struct gpu_ops *gops); -void vgpu_init_debug_ops(struct gpu_ops *gops); -void vgpu_init_tsg_ops(struct gpu_ops *gops); -#if defined(CONFIG_GK20A_CYCLE_STATS) -void vgpu_init_css_ops(struct gpu_ops *gops); -#endif -void vgpu_init_ce2_ops(struct gpu_ops *gops); +u32 vgpu_ce_get_num_pce(struct gk20a *g); int vgpu_init_mm_support(struct gk20a *g); int vgpu_init_gr_support(struct gk20a *g); int vgpu_init_fifo_support(struct gk20a *g); @@ -112,15 +103,17 @@ int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value); int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, size_t size_out); -void vgpu_init_hal_common(struct gk20a *g); int vgpu_gm20b_init_hal(struct gk20a *g); int vgpu_gp10b_init_hal(struct gk20a *g); -void vgpu_init_dbg_session_ops(struct gpu_ops *gops); int vgpu_init_gpu_characteristics(struct gk20a *g); void vgpu_create_sysfs(struct device *dev); void vgpu_remove_sysfs(struct device *dev); +int vgpu_read_ptimer(struct gk20a *g, u64 *value); +int vgpu_get_timestamps_zipper(struct gk20a *g, + u32 source_id, u32 count, + struct nvgpu_cpu_time_correlation_sample *samples); #else static inline int vgpu_pm_prepare_poweroff(struct device *dev) { @@ -169,29 +162,6 @@ static inline int vgpu_fifo_isr(struct gk20a *g, { return 0; } -static inline void vgpu_init_fifo_ops(struct gpu_ops *gops) -{ -} -static inline void vgpu_init_gr_ops(struct gpu_ops *gops) -{ -} -static inline void vgpu_init_ltc_ops(struct gpu_ops *gops) -{ -} -static inline void vgpu_init_mm_ops(struct gpu_ops *gops) -{ -} -static inline void vgpu_init_debug_ops(struct gpu_ops *gops) -{ -} -#if defined(CONFIG_GK20A_CYCLE_STATS) -static inline void vgpu_init_css_ops(struct gpu_ops *gops) -{ -} -#endif -static inline void vgpu_init_ce2_ops(struct gpu_ops *gops) -{ -} static inline int vgpu_init_mm_support(struct gk20a *g) { return -ENOSYS;