diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c
index e2b764096..591c26e0d 100644
--- a/drivers/gpu/nvgpu/clk/clk.c
+++ b/drivers/gpu/nvgpu/clk/clk.c
@@ -27,11 +27,11 @@
 #include <nvgpu/pmuif/ctrlvolt.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/pmuif/ctrlperf.h>
+#include <nvgpu/pmu/pstate.h>
 
 #include "clk.h"
 #include <nvgpu/timers.h>
 #include "volt/volt.h"
-#include "pstate/pstate.h"
 
 #define BOOT_GPC2CLK_MHZ  2581U
 #define BOOT_MCLK_MHZ     3003U
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c
index 60a3afddb..0ebba65c2 100644
--- a/drivers/gpu/nvgpu/clk/clk_arb.c
+++ b/drivers/gpu/nvgpu/clk/clk_arb.c
@@ -33,9 +33,9 @@
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/pmu/pstate.h>
 
 #include "clk/clk.h"
-#include "pstate/pstate.h"
 #include "lpwr/lpwr.h"
 #include "volt/volt.h"
 
diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
index b8f0ce2e1..532bf9afd 100644
--- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c
+++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
@@ -40,13 +40,12 @@
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel_sync.h>
+#include <nvgpu/pmu/pstate.h>
 
 #include <trace/events/gk20a.h>
 
 #include "gk20a/ce2_gk20a.h"
 
-#include "pstate/pstate.h"
-
 void __nvgpu_check_gpu_state(struct gk20a *g)
 {
 	u32 boot_0 = 0xffffffffU;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index da1b63547..ee6a098c8 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -30,12 +30,13 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/boardobj.h>
 #include <nvgpu/boardobjgrp.h>
+#include <nvgpu/pmu/pstate.h>
 
 #include "clk/clk.h"
 #include "clk/clk_vin.h"
 #include "clk/clk_fll.h"
 #include "volt/volt.h"
-#include "pstate/pstate.h"
+#include "volt/volt_pmu.h"
 
 /* PMU NS UCODE IMG */
 #define NVGPU_PMU_NS_UCODE_IMAGE	"gpmu_ucode.bin"
diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
index 643ba0e84..e315a169d 100644
--- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
@@ -28,13 +28,15 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/string.h>
+#include <nvgpu/pmu/pstate.h>
 
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 #include "os/linux/os_linux.h"
 #endif
-#include "pstate/pstate.h"
 #include "gp106/mclk_gp106.h"
+#include "clk/clk.h"
+#include "clk/clk_mclk.h"
 
 #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
 #include <nvgpu/hw/gp106/hw_fb_gp106.h>
diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
index f1ece0f9b..2c805b9f3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
@@ -35,9 +35,9 @@ struct gk20a;
 #include <nvgpu/log.h>
 #include <nvgpu/barrier.h>
 #include <nvgpu/cond.h>
+#include <nvgpu/pmu/pstate.h>
 
 #include "clk/clk.h"
-#include "pstate/pstate.h"
 #include "lpwr/lpwr.h"
 #include "volt/volt.h"
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pstate.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pstate.h
new file mode 100644
index 000000000..0e750ec68
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pstate.h
@@ -0,0 +1,73 @@
+/*
+ * general p state infrastructure
+ *
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_PMU_PSTATE_H
+#define NVGPU_PMU_PSTATE_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/boardobj.h>
+#include <nvgpu/boardobjgrp_e32.h>
+
+#define CTRL_PERF_PSTATE_P0		0U
+#define CTRL_PERF_PSTATE_P5		5U
+#define CTRL_PERF_PSTATE_P8		8U
+
+#define CLK_SET_INFO_MAX_SIZE		(32U)
+
+struct gk20a;
+
+struct clk_set_info {
+	u32 clkwhich;
+	u32 nominal_mhz;
+	u16 min_mhz;
+	u16 max_mhz;
+};
+
+struct clk_set_info_list {
+	u32 num_info;
+	struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
+};
+
+struct pstate {
+	struct boardobj super;
+	u32 num;
+	u8 lpwr_entry_idx;
+	struct clk_set_info_list clklist;
+};
+
+struct pstates {
+	struct boardobjgrp_e32 super;
+	u32  num_levels;
+	struct nvgpu_cond pstate_notifier_wq;
+	u32 is_pstate_switch_on;
+	struct nvgpu_mutex pstate_mutex; /* protect is_pstate_switch_on */
+};
+
+int gk20a_init_pstate_support(struct gk20a *g);
+void gk20a_deinit_pstate_support(struct gk20a *g);
+int gk20a_init_pstate_pmu_support(struct gk20a *g);
+struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num,
+		u32 clkwhich);
+struct pstate *pstate_find(struct gk20a *g, u32 num);
+
+#endif /* NVGPU_PMU_PSTATE_H */
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index 2975aded3..11f0de40c 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -25,9 +25,9 @@
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/string.h>
+#include <nvgpu/pmu/pstate.h>
 
 #include "gp106/bios_gp106.h"
-#include "pstate/pstate.h"
 #include "pmu_perf/pmu_perf.h"
 #include "lpwr.h"
 
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c
index c58e5a0e7..e78d09dea 100644
--- a/drivers/gpu/nvgpu/lpwr/rppg.c
+++ b/drivers/gpu/nvgpu/lpwr/rppg.c
@@ -22,9 +22,9 @@
 
 #include <nvgpu/pmu.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/pmu/pstate.h>
 
 #include "gp106/bios_gp106.h"
-#include "pstate/pstate.h"
 #include "lpwr/rppg.h"
 
 static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c b/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c
index d8af9a768..d8fc3038b 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c
@@ -37,9 +37,9 @@
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/enabled.h>
+#include <nvgpu/pmu/pstate.h>
 
 #include "clk/clk.h"
-#include "pstate/pstate.h"
 #include "lpwr/lpwr.h"
 #include "volt/volt.h"
 
diff --git a/drivers/gpu/nvgpu/pmu_perf/change_seq.c b/drivers/gpu/nvgpu/pmu_perf/change_seq.c
index c104177e2..bb0cbf5ba 100644
--- a/drivers/gpu/nvgpu/pmu_perf/change_seq.c
+++ b/drivers/gpu/nvgpu/pmu_perf/change_seq.c
@@ -26,9 +26,10 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/pmuif/ctrlclk.h>
+#include <nvgpu/pmu/pstate.h>
 
+#include "clk/clk.h"
 #include "clk/clk_domain.h"
-#include "pstate/pstate.h"
 #include "pmu_perf.h"
 
 #include "change_seq.h"
diff --git a/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c b/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c
index 3d0d4f60e..e3a3ab6a5 100644
--- a/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c
+++ b/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c
@@ -26,6 +26,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/gk20a.h>
 
+#include "clk/clk.h"
 #include "perf_gv100.h"
 #include "pmu_perf/pmu_perf.h"
 
diff --git a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h
index bb8e63b50..302004e33 100644
--- a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h
+++ b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h
@@ -22,10 +22,11 @@
 #ifndef NVGPU_PERF_H
 #define NVGPU_PERF_H
 
+#include <nvgpu/pmu/pstate.h>
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
+
 #include "vfe_equ.h"
 #include "vfe_var.h"
-#include "pstate/pstate.h"
 #include "volt/volt.h"
 #include "lpwr/lpwr.h"
 #include "change_seq.h"
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index 45a145403..8219b66fd 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -31,9 +31,10 @@
 #include "pmu_perf/pmu_perf.h"
 #include "pmu_perf/change_seq.h"
 #include "pmgr/pmgr.h"
-#include "pstate/pstate.h"
 #include "therm/thrm.h"
 
+#include "pstate.h"
+
 static int pstate_sw_setup(struct gk20a *g);
 
 void gk20a_deinit_pstate_support(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h
index f00591a4e..23e4d5aa3 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.h
+++ b/drivers/gpu/nvgpu/pstate/pstate.h
@@ -1,7 +1,7 @@
 /*
  * general p state infrastructure
  *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,54 +21,9 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef NVGPU_PSTATE_H
-#define NVGPU_PSTATE_H
-
-#include "clk/clk.h"
+#ifndef NVGPU_PSTATE_PSTATE_H
+#define NVGPU_PSTATE_PSTATE_H
 
 #define CTRL_PERF_PSTATE_TYPE_3X	0x3U
 
-#define CTRL_PERF_PSTATE_P0		0U
-#define CTRL_PERF_PSTATE_P5		5U
-#define CTRL_PERF_PSTATE_P8		8U
-
-#define CLK_SET_INFO_MAX_SIZE		(32U)
-
-struct gk20a;
-
-struct clk_set_info {
-	u32 clkwhich;
-	u32 nominal_mhz;
-	u16 min_mhz;
-	u16 max_mhz;
-};
-
-struct clk_set_info_list {
-	u32 num_info;
-	struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
-};
-
-struct pstate {
-	struct boardobj super;
-	u32 num;
-	u8 lpwr_entry_idx;
-	struct clk_set_info_list clklist;
-};
-
-struct pstates {
-	struct boardobjgrp_e32 super;
-	u32  num_levels;
-	struct nvgpu_cond pstate_notifier_wq;
-	u32 is_pstate_switch_on;
-	struct nvgpu_mutex pstate_mutex; /* protect is_pstate_switch_on */
-};
-
-int gk20a_init_pstate_support(struct gk20a *g);
-void gk20a_deinit_pstate_support(struct gk20a *g);
-int gk20a_init_pstate_pmu_support(struct gk20a *g);
-
-struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num,
-		u32 clkwhich);
-struct pstate *pstate_find(struct gk20a *g, u32 num);
-
-#endif /* NVGPU_PSTATE_H */
+#endif /* NVGPU_PSTATE_PSTATE_H */