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gpu: nvgpu: fixing MISRA violations

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- Rule 4.12
  Dynamic memory allocation shall not be used.

- Rule 8.6
  "gp10b_device_info_parse_data" is declared but never defined

- Rule 5.7
  A tag name shall be a unique identifier

JIRA NVGPU-6536

Change-Id: I2f234d4aadd217f13b51e4dcadfa13d284a3750f
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2582076
(cherry picked from commit 7394eedcdfd606a4687adba1ce82e96b5d6e23f8)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2677542
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
srajum
2021-08-24 12:29:26 +05:30
committed by mobile promotions
parent 8be6ab837a
commit 585c3ab1c1
5 changed files with 17 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -1,7 +1,7 @@
/*
* GM20B Graphics
*
* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -54,7 +54,9 @@
#include <nvgpu/pmu/pmu_pstate.h>
#endif
#include <nvgpu/therm.h>
#ifdef CONFIG_NVGPU_CLK_ARB
#include <nvgpu/clk_arb.h>
#endif
#include <nvgpu/grmgr.h>
#ifdef CONFIG_NVGPU_POWER_PG
#include <nvgpu/pmu/pmu_pg.h>

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -31,7 +31,9 @@
#include <nvgpu/pmu/pmu_pstate.h>
#endif
#include <nvgpu/therm.h>
#ifdef CONFIG_NVGPU_CLK_ARB
#include <nvgpu/clk_arb.h>
#endif
#include <nvgpu/fuse.h>
#include <nvgpu/pbdma.h>
#include <nvgpu/preempt.h>

4
drivers/gpu/nvgpu/hal/top/top_gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -30,8 +30,10 @@
struct gk20a;
struct nvgpu_device;
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
int gp10b_device_info_parse_data(struct gk20a *g, u32 table_entry, u32 *inst_id,
u32 *pri_base, u32 *fault_id);
#endif
int gp10b_get_device_info(struct gk20a *g, struct nvgpu_device *dev_info,
u32 engine_type, u32 inst_id);
#endif

4
drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,7 +31,9 @@ struct nvgpu_list_node;
#include <nvgpu/boardobjgrpmask.h>
#include <nvgpu/list.h>
#include <nvgpu/nvgpu_mem.h>
#ifdef CONFIG_NVGPU_DGPU
#include <nvgpu/pmu/super_surface.h>
#endif
#include <nvgpu/flcnif_cmn.h>
/* Dependency of this include will be removed in further CL */
#include "../../common/pmu/boardobj/boardobj.h"

12
drivers/gpu/nvgpu/os/posix/kmem.c
View File

@@ -74,9 +74,9 @@ struct nvgpu_kmem_cache *nvgpu_kmem_cache_create(struct gk20a *g, size_t size)
}
#endif
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 21_3), "TID-1131")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 4_12), "TID-1129")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Directive, 4_12), "TID-1129")
cache = malloc(sizeof(struct nvgpu_kmem_cache));
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 4_12))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Directive, 4_12))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 21_3))
if (cache == NULL) {
@@ -112,9 +112,9 @@ void *nvgpu_kmem_cache_alloc(struct nvgpu_kmem_cache *cache)
}
#endif
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 21_3), "TID-1131")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 4_12), "TID-1129")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Directive, 4_12), "TID-1129")
ptr = malloc(cache->size);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 4_12))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Directive, 4_12))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 21_3))
if (ptr == NULL) {
@@ -153,9 +153,9 @@ void *nvgpu_kmalloc_impl(struct gk20a *g, size_t size, void *ip)
* calls).
*/
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 21_3), "TID-1131")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 4_12), "TID-1129")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Directive, 4_12), "TID-1129")
ptr = malloc(size);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 4_12))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Directive, 4_12))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 21_3))
if (ptr == NULL) {