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gpu: nvgpu: Add thermal module support
The following CL contains the following VBIOS thermal table parsing and PMU interface support. 1) Thermal device table 2) Thermal channel table JIRA DNVGPU-130 Change-Id: Ie3abab4bf099a022b1b59db96811c2ed44079519 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1240630 (cherry picked from commit 814962a4be0a8cd0cddc7bc5211c62308ab1fea2) Reviewed-on: http://git-master/r/1246210 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
committed by
Deepak Nibade
parent
2f4405ddcb
commit
58b85dd106
@@ -788,4 +788,58 @@ struct vbios_voltage_policy_table_1x_entry {
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#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \
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0
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#define VBIOS_THERM_DEVICE_VERSION_1X 0x10
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#define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004
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struct therm_device_1x_header {
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u8 version;
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u8 header_size;
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u8 table_entry_size;
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u8 num_table_entries;
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} ;
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struct therm_device_1x_entry {
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u8 class_id;
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u8 param0;
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u8 flags;
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} ;
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#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01
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#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF
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#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0
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#define VBIOS_THERM_CHANNEL_VERSION_1X 0x10
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#define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009
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struct therm_channel_1x_header {
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u8 version;
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u8 header_size;
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u8 table_entry_size;
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u8 num_table_entries;
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u8 gpu_avg_pri_ch_idx;
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u8 gpu_max_pri_ch_idx;
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u8 board_pri_ch_idx;
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u8 mem_pri_ch_idx;
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u8 pwr_supply_pri_ch_idx;
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};
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struct therm_channel_1x_entry {
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u8 class_id;
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u8 param0;
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u8 param1;
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u8 param2;
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u8 flags;
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};
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#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01
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#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF
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#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0
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#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFF
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#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0
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#endif
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