gpu: nvgpu: Add CHANNEL_SETUP_BIND IOCTL

For a long time now, the ALLOC_GPFIFO_EX channel IOCTL has done much
more than just gpfifo allocation, and its signature does not match
support that's needed soon. Add a new one called SETUP_BIND to hopefully
cover our future needs and deprecate ALLOC_GPFIFO_EX.

Change nvgpu internals to match this new naming as well.

Bug 200145225
Bug 200541476

Change-Id: I766f9283a064e140656f6004b2b766db70bd6cad
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1835186
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
(cherry-picked from e0c8a16c8d
in dev-main)
Reviewed-on: https://git-master.nvidia.com/r/2169882
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2019-08-07 11:57:28 +05:30
committed by mobile promotions
parent ae175e45ed
commit 58ee7561f7
8 changed files with 128 additions and 77 deletions

View File

@@ -1312,7 +1312,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
struct channel_gk20a *ch;
struct tsg_gk20a *tsg;
struct gr_gk20a *gr = &g->gr;
struct nvgpu_gpfifo_args gpfifo_args;
struct nvgpu_setup_bind_args setup_bind_args;
int err = 0;
u64 vaddr;
@@ -1351,17 +1351,16 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
err = gk20a_tsg_bind_channel(tsg, ch);
if (err) {
nvgpu_err(g, "cde: unable to bind to tsg");
goto err_alloc_gpfifo;
goto err_setup_bind;
}
gpfifo_args.num_entries = 1024;
gpfifo_args.num_inflight_jobs = 0;
gpfifo_args.flags = 0;
/* allocate gpfifo (1024 should be more than enough) */
err = gk20a_channel_alloc_gpfifo(ch, &gpfifo_args);
setup_bind_args.num_gpfifo_entries = 1024;
setup_bind_args.num_inflight_jobs = 0;
setup_bind_args.flags = 0;
err = nvgpu_channel_setup_bind(ch, &setup_bind_args);
if (err) {
nvgpu_warn(g, "cde: unable to allocate gpfifo");
goto err_alloc_gpfifo;
nvgpu_warn(g, "cde: unable to setup channel");
goto err_setup_bind;
}
/* map backing store to gpu virtual space */
@@ -1399,7 +1398,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
err_init_cde_img:
nvgpu_gmmu_unmap(ch->vm, &g->gr.compbit_store.mem, vaddr);
err_map_backingstore:
err_alloc_gpfifo:
err_setup_bind:
nvgpu_vm_put(ch->vm);
err_commit_va:
err_get_gk20a_channel: